EP80579 Datasheet, PDF (863/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
23.3.3.7 Offset 118h: PxCMD[0-1] – Port [0-1] Command Register
Table 23-62. Offset 118h: PxCMD[0-1] – Port [0-1] Command Register (Sheet 1 of 3)
Description:
View: PCI
BAR: ABAR
Bus:Device:Function: 0:31:2
Offset Start: 118h, 198h
Offset End: 11Bh, 19Bh
Size: 32 bit
Default: Variable
Power Well: Core
Bit Range
Bit Acronym
Bit Description
Sticky
Bit Reset
Value
Interface Communication Control (ICC): This is a four
bit field which can be used to control reset and power states
of the interface. If the Link layer is currently in the L_IDLE
state, writes to this field shall cause the HBA to initiate a
transition to the interface power management state
requested. If the Link layer is not currently in the L_IDLE
state, writes to this field shall have no effect.
Bit Access
31 : 28
Value
Definition
Fh–7h Reserved
Slumber: This will cause the HBA to request a
6h
transition of the interface to the Slumber state. The
SATA device may reject the request and the
interface will remain in its current state.
5h–3h Reserved
Partial: This will cause the HBA to request a
ICC
2h
transition of the interface to the Partial state. The
SATA device may reject the request and the
interface will remain in its current state.
1h
Active: This will cause the HBA to request a
transition of the interface into the active state.
No-Op / Idle: When software reads this value, it
indicates the HBA is ready to accept a new
0h
interface control command, although the transition
to the previously selected state may not yet have
occurred.
0h
RW
When system software writes a non-reserved value other
than No-Op (0h), the HBA will perform the action and
update this field back to Idle (0h).
If software writes to this field to change the state to a state
the link is already in (i.e. interface is in the active state and
a request is made to go to the active state), the HBA will
take no action and return this field to Idle. If the interface is
in a low power state and the software wants to transition to
a different low power state, software must first bring the
link to active and then initiate the transition to the desired
low power state.
Aggressive Slumber / Partial (ASP): When set, and the
ALPE bit is set, the HBA will aggressively enter the Slumber
27
ASP
state when it clears the PxCI register and the PxSACT
register is cleared. When cleared, and the ALPE bit is set,
the HBA will aggressively enter the Partial state when it
clears the PxCI register and the PxSACT register is cleared.
Aggressive Link Power Management Enable (ALPE):
26
ALPE
When set, the HBA will aggressively enter a lower link
power state (Partial or Slumber) based upon the setting of
the ASP bit.
Drive LED on ATAPI Enable (DLAE): When set, the HBA
will drive the LED pin active for commands regardless of the
25
DLAE
state of PxCMD.ATAPI. When cleared, the HBA will only
drive the LED pin active for commands if PxCMD.ATAPI is
set to ‘0’.
0h
RW
0h
RW
0h
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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