EP80579 Datasheet, PDF (1303/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 35-115.Offset F0h: MCID: Message Signalled Interrupt Capability ID Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: M:6:0
Offset Start: F0h
Offset End: F0h
Size: 8 bit
Default: 05h
Power Well: Core
Bit Range Bit Acronym
Bit Description
07 : 00
MCID
Capability ID: PCI SIG assigned capability record ID
(05h, MSI capability)
Sticky
Bit Reset
Value
Bit Access
05h
RO
35.10.1.27 Offset F1h: MCP – Message Signalled Interrupt Next Capability Pointer
Register
Table 35-116.Offset F1h: MCP: Message Signalled Interrupt Next Capability Pointer
Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: M:6:0
Offset Start: F1h
Offset End: F1h
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range
07 : 00
Bit Acronym
Bit Description
Sticky
MCP
Next Capability Pointer: Hardwired to 0 to indicate this
is the last capability.
Bit Reset
Value
0h
Bit Access
RO
35.10.1.28 Offset F2h: MCTL – Message Signalled Interrupt Control Register
Table 35-117.Offset F2h: MCTL: Message Signalled Interrupt Control Register (Sheet 1 of
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: M:6:0
Offset Start: F2h
Offset End: F3h
Size: 16 bit
Default: 0000h
Power Well: Core
Bit Range
15 : 09
08
07
Bit Acronym
Bit Description
Sticky
Reserved
MC
C64
Reserved
Per-Vector Masking Capable: Hardwired to 0 to indicate
the device is not capable of per-vector masking.
64 bit Address Capable: Hardwired to 0 to indicate the
device does not generate 64b message addresses.
Bit Reset
Value
0h
0h
0h
Bit Access
RO
RO
RO
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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