EP80579 Datasheet, PDF (1617/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Register Name:
SSITR
Block
Base Address:
N/A
Offset Address
0x0C
Reset Value
00000000
Register Description: SSP Interrupt Test Register
Access: (See below.)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved
Table 40-6. Offset 0Ch: SSITR - SSP Interrupt Test Register Details
Description:
View: PCI
BAR: CSRBAR
Bus:Device:Function: M:6:0
Offset Start: 0Ch
Offset End: 0Fh
Size: 32 bit
Default: 00000000
Power Well: Core
Bit Range
31 :08
07
06
05
04 :00
Bit Acronym
Bit Description
Reserved
TROR
TRFS
TTFS
Reserved
Reserved
Test Receive FIFO overrun (ROR)
Test Receive FIFO service request (RFS)
Test Transmit FIFO service request (TFS)
Reserved
Sticky
Bit Reset
Value
0h
0b
0b
0b
0h
Bit Access
RV
RW
RW
RW
RV
40.4.5
40.4.5.1
SSP Data Register
Offset 10h: SSDR - SSP Data Register Details
The SSP Data Register (SSDR) is a block of 32-bit locations that can be accessed by 32-
bit data transfers. Transfers can be from 1 to 8 words. The SSDR represents two
physical registers: the first is temporary storage for data on its way out through the
Transmit FIFO, the other is temporary storage for data coming in through the Receive
FIFO.
As the register is accessed by the system, FIFO control logic transfers data
automatically between register and FIFO as fast as the system moves it. Data in the
FIFO shifts up or down to accommodate the new word (unless it’s an attempted WRITE
to a full Transmit FIFO). Status bits are available to show the system whether either
buffer is full, above/below a programmable threshold, or empty.
For outbound data transfers (WRITE from system to SSP peripheral), the register may
be loaded (written) by the system processor anytime the register is empty.
When a data size of less than 16-bits is selected, the user should not left-justify data
written to the transmit FIFO. Transmit logic left-justifies the data and ignores any
unused bits. Received data less than 16-bits is automatically right-justified in the
receive buffer. When the SSP is programmed for National Microwire frame format, the
default size for transmit data is 8-bits (the most significant byte is ignored), the receive
data size is controlled by the programmer using the DSS field in SSCR0.
The following table shows the location of the SSP data register. Note that both FIFOs
are cleared when the block is reset or by writing a zero to SSE (SSP disabled).
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
1617