EP80579 Datasheet, PDF (1479/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
37.6.4.3
Note:
FCRTH – Flow Control Receive Threshold High Register
This register contains the receive threshold used to determine when to send an XOFF
packet. It counts in units of bytes. This value must be at least 8 bytes less than the
maximum number of bytes allocated to the Receive Packet Buffer (PBA, RXA), and the
lower 3 bits must be programmed to 0 (8B granularity). Whenever the receive FIFO
reaches the fullness indicated by FCRTH.RTH, hardware transmits a PAUSE frame if the
transmission of flow control frames is enabled.
Flow control reception/transmission are negotiated capabilities by the Auto-Negotiation
process. When the device is manually configured, flow control operation is determined
by the CTRL.RFCE & CTRL.TFCE.
Table 37-52. FCRTH: Flow Control Receive Threshold High Register
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 2168h
Offset End: 216Bh
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 2168h
Offset End: 216Bh
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 2168h
Offset End: 216Bh
Size: 32 bits
Default: 00000000h
GbE0: Core
Power Well: Gbe1/2:
Core
Bit Range
31
Bit Acronym
Bit Description
Sticky
XFCE
External Flow Control Enabled
0b = Disabled.
1b = Enabled.
Allows the Ethernet controller to send XOFF and XON
frames based on external pins XOFF and XON. The
transmission of pause frames must be also enabled
through the CTRL.TFCE control bit. When the XOFF signal
is asserted high, the Ethernet controller transmits a single
XOFF frame. The assertion of XON (after deassertion of
XOFF) initiates an XON frame transmission, if enabled by
FCRTL.XONE. The assertion/deassertion of XON is required
between assertions of XOFF in order to send another XOFF
frame.
This behavior also provides a built-in hysteresis
mechanism.
Bit Reset
Value
0h
Bit Access
RW
30 : 16
15 : 03
02 : 00
Rsvd
RTH
0
Note:
The EP80579 does not have external XON/XOFF
pins and therefore does not support external flow
control enable. This bit must be set to 0 for correct
operation.
Reserved
Receive Threshold High. FIFO high water mark for flow
control transmission.
Writes are ignored, reads return 0.
0h
RV
0h
RW
0h
RV
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
1479