EP80579 Datasheet, PDF (108/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
b. Agents in the IA-32 core may access AIOC-Direct memory (non-coherent) via uncacheable 1, 2 or 4-byte IA
loads/store, IA MMX 8-byte MOVQ instructions or 64-byte DMA transfers. While such IA-32 core accesses to
AIOC-Direct memory are not ordered with respect to other ASU memory traffic, the AIOC-Direct memory
supports limited one-way communication in which IA agent (or the Internal PCI agent) is the sole writer and
the internal PCI agent (or the IA agent) views such memory locations as read-only. Hardware will ensure that
self-aligned 1,2, 4, 8 and 64-byte updates will be atomically visible to all readers.
The EP80579 allows signaling to occur between IA, AIOC complex, and externally-
attached agents in the appropriate native signaling format.
The EP80579 supports basic producer/consumer behavior between agents.
Because the AIOC complex devices are exposed to the IA platform as PCI devices, they
follow PCI ordering semantics when interacting with IA. This enables two fundamental
producer/consumer models in coherent memory: the polled and interrupt methods.
For the Polled method:
1. Producer writes data to location “X” in Coherent Memory.
2. Producer sets flag to location “Y” in Coherent Memory
3. Consumer waits for flag to be set in Coherent Memory
4. Consumer read data from location “X” in Coherent Memory
To ensure this behavior, agents generating traffic into the IMCH must ensure that the
writes originating from an agent are globally observable in the same order. In the
above case X and Y must be globally observable in the same order.
For the Interrupt method:
1. Producer writes data to location “X” in Coherent Memory.
2. Producer generates an interrupt to Consumer (asynchronous signal)
3. Consumer reads interrupt status from Producer’s address space. Consumer waits
for read to complete before issuing the next transaction.
4. Consumer reads data from location “X” in Coherent Memory
To ensure this behavior, an MMIO read issued to the PCI device (item 3 above) after a
write that originated from this PCI device (item 1 above) must not complete out of
order. The read completion must push ahead (flush) the write.
Also the MMIO read (item 3 above) should be to a location that is in the device. In the
EP80579, it should not be to the PCI configuration registers but the device registers
pointed to by the PCI BAR¹. This ensures that IA device driver software for the
EP80579 is not required to include explicit memory fence operations to enable
producer-consumer synchronization for interrupt handling. Examples:
1. GigE ⇔ IA : GigE placing received data in coherent DRAM and interrupting IA, IA
issuing a GigE CSR read, whose read completion must serialize the received DRAM
data stream.
2. TDM ⇔ IA : TDM placing received data in coherent DRAM, then interrupting the IA,
then IA gets a pointer to the data. An IA pointer dereference from the IA must see
the TDM DRAM data.
3. ASU ⇔ IA : ASU placing data in coherent DRAM, then interrupting the IA, then IA
gets a pointer to the data. An IA pointer dereference from the IA must see the ASU
DRAM data.
1. The reason for this requirement is that the MCH config bus used to access the PCI configuration registers does not serialize
the EP80579 internal PCI bus.
Intel^® EP80579 Integrated Processor Product Line Datasheet
108
August 2009
Order Number: 320066-003US