EP80579 Datasheet, PDF (382/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
15.3.3
15.3.3.1
Note:
15.3.3.2
PCI Express Interface Power Management
In PCI Express, the traditional bus (B*) power states assigned to system buses are
replaced by link (L*) power states, which are largely managed by hardware without
software intervention. Entry into and out of these states may be initiated by two
distinct mechanisms:
• traditional PCI-PMI type software managed state changes
• non-traditional PCI Express autonomous hardware state changes
The latter transition type is designated “Active State Power Management,” (ASPM) and
included with the PCI Express Interface Specification, Rev. 1.0a.
PCI Express Link Power State Definitions
Support for all of the following PCI Express link power states is required for PCI Express
Specification compatibility:
The IMCH does not support all PCI Express link power states.
• L0 – Active state with all operations enabled (default state after platform
initialization).
• L0s –Low latency, energy saving standby state, disabling exchange of both
transaction layer packets and device link layer messages. This state is used
exclusively by the ASPM PCI Express function, with entry and exit managed
autonomously by PCI Express interface hardware.
• L1 – (Only supported in software managed state changes) Moderate to high
latency, very low power, standby state, disabling exchange of both transaction layer
packets and device link layer messages. Entered when the downstream device is
programmed to a device power state below the D0 active state, or optionally under
hardware control during ASPM. The clock remains active in L1, and exit from this
state may be initiated by either the upstream or the downstream device.
• L2/L3 Ready – Staging point for removal of main power and clocking. New
intermediate state not directly related to PCI PM D-state transitions, nor to ASPM.
Hand-shaking lands the link in this state in anticipation of power removal, at which
point the link moves to either L2 or L3 depending upon the presence of Vaux.
• L2 – High latency, very low deep sleep state, disabling exchange of transaction
layer packets and device link layer messages. L2 is characterized by removal of
clocking and main power, but presence of Vaux power. Exit is initiated by restoring
clocking and power, and full initialization.
• L3 – High latency, link off state with power, Vaux, and clock reference removed.
Exit is initiated by restoring clocking and power, and full initialization.
The IMCH is fully compliant with the PCI Express Specification, but does not support
the optional L1 state via the ASPM mechanism. Refer to the PCI Express* Interface
Specification, Rev. 1.0a for further detail on the link states and specific information on
entry and exit mechanisms.
Software Controlled PCI Express Link States
Software managed device power state changes do not explicitly control the power L-
state of PCI Express links. Instead the L-state is inferred by hardware from the PCI-PMI
power state of the devices attached to that link. When PM software transitions a PCI
Express device to a low power state, that device automatically negotiates with
hardware to bring its upstream link into the appropriate link power state.
No link is allowed to be in a link power state “below” that which is dictated by its
attached components.
Intel^® EP80579 Integrated Processor Product Line Datasheet
382
August 2009
Order Number: 320066-003US