EP80579 Datasheet, PDF (1103/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Figure 28-1. Coprocessor Error Timing Diagram
FERR#
Internal IRQ13
I/O Write to F0h
IGNNE#
If COPROC_ERR_EN is not set, then the assertion of FERR# does not generate an
internal IRQ13, nor writes to F0h generate IGNNE#.
Non-Maskable Interrupts (NMIs) can be generated by several sources that are
described in Table 28-9.
Table 28-9. NMI Sources
Cause of NMI
Comment
SERR# goes active (either internally, externally via
SERR# signal, or via message from IMCH)
ISA IOCHK# goes active via SERIRQ# stream (legacy
system Error)
Watch Dog Timer (LPC bus: logical device 6) first
stage 35-bit Down Counter reaches zero.
IOCHK# is a legacy signal. CMI does not have this
pin, but it may be on the platform.
Enabled by WDT_INT_TYPE field in the WDT
Configuration Register.
28.2.3
INTR# (Interrupt Signals)
The behavior of the INTR signal and I/O APIC interrupt signals are described in
Chapter 30.0, “Interrupts”.
28.2.4
STPCLK# and CPUSLP# (Stop Clock Request and Processor
Sleep Signals)
These active-low signals are controlled by the power management logic. See
Chapter 27.0, “Power Management” for more details.
28.2.5
Enhanced Intel SpeedStep Technology (EIST) Signals
Enhanced Intel SpeedStep Technology (EIST) is not supported.
28.2.6
DPSLP# (Deeper Sleep)
DPSLP# is not supported.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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