EP80579 Datasheet, PDF (465/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 16-72. Offset 58h: NSI_SERRCMD - NSI SERR Command Register (Sheet 2 of 2)
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:1
Offset Start: 58h
Offset End: 5Bh
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range Bit Acronym
Bit Description
14
13
12
11
10
09
08
07
06
05
04 : 03
02
01
00
Reserved Reserved
RNRO_SERR
Generate SERR for NSI Error 13: Generate SERR
whenever bit 13 of NSI _FERR or NSI _NERR is set.
0 = Disable
1 = Enable
BDLLP_SERR
Generate SERR for NSI Error 12: Generate SERR
whenever bit 12 of NSI _FERR or NSI _NERR is set.
0 = Disable
1 = Enable
BTLP_SERR
Generate SERR for NSI Error 11: Generate SERR
whenever bit 11 of NSI _FERR or NSI _NERR is set.
0 = Disable
1 = Enable
Reserved Reserved
RCVRE_SERR
Generate SERR for NSI Error 9: Generate SERR
whenever bit 9 of NSI _FERR or NSI _NERR is set.
0 = Disable
1 = Enable
Reserved Reserved
FEMR_SERR
Generate SERR for NSI Error 7: Generate SERR
whenever bit 7 of NSI _FERR or NSI _NERR is set.
0 = Disable
1 = Enable
NEMR_SERR
Generate SERR for NSI Error 6: Generate SERR
whenever bit 6 of NSI _FERR or NSI _NERR is set.
0 = Disable
1 = Enable
CEMR_SERR
Generate SERR for NSI Error 5: Generate SERR
whenever bit 5 of NSI _FERR or NSI _NERR is set.
0 = Disable
1 = Enable
Reserved Reserved
PED_SERR
Generate SERR for NSI Error 2: Generate SERR
whenever bit 2 of NSI _FERR or NSI _NERR is set.
0 = Disable
1 = Enable
Reserved Reserved
LD_SERR
Generate SERR for NSI Error 0: Generate SERR
whenever bit 0 of NSI _FERR or NSI _NERR is set.
0 = Disable
1 = Enable
Sticky
Bit Reset
Value
0b
Bit Access
0b
RW
0b
RW
0b
RW
0b
0b
RW
0b
0b
RW
0b
RW
0b
RW
0b
0b
RW
0b
0b
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
465