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Intel^® EP80579 Integrated Processor
10.7
IICH Register and Memory Mappings
This section covers CMI’s IICH various address decoding ranges.
This section is for background purposes, and must not to be considered by
implementers and validators as part of the behavioral definition of CMI. Each decode
range is described elsewhere in the section associated with the corresponding function.
10.7.1
I/O Map
The I/O map is divided into separate types. Fixed ranges cannot be moved, but in some
cases can be disabled. Variable ranges can be moved and can also be disabled.
10.7.1.1
Fixed I/O Address Ranges
Table 10-17 shows the Fixed I/O decode ranges from the IA-32 core perspective. Note
that for each I/O range, there may be separate behavior for reads and writes. Cycles
that go to target ranges that are marked as Reserved will not be decoded, and are
passed to PCI to PCI Bridge where they are dropped.
Address ranges that are not listed or marked reserved are NOT positively decoded by
the IICH (unless assigned to one of the variable ranges). In subtractive mode, I/O
ranges that are not otherwise decoded are forwarded to PCI to PCI Bridge where they
are dropped.
Table 10-17. Fixed I/O Ranges Decoded by IICH (Sheet 1 of 3)
I/O Address
00h – 08h
09h – 0Eh
0Fh
10h – 18h
19h – 1Eh
1Fh
20h – 21h
24h – 25h
28h – 29h
2Ch – 2Dh
2E – 2F
30h – 31h
34h – 35h
38h – 39h
3Ch – 3Dh
40h – 42h
43h
4E – 4F
50h – 52h
53h
60h
Read Target
DMA Controller
RESERVED
DMA Controller
DMA Controller
RESERVED
DMA Controller
Interrupt Controller
Interrupt Controller
Interrupt Controller
Interrupt Controller
LPC SIO
Interrupt Controller
Interrupt Controller
Interrupt Controller
Interrupt Controller
Timer/Counter
RESERVED
LPC SIO
Timer/Counter
RESERVED
Microcontroller
Write Target
DMA Controller
DMA Controller
DMA Controller
DMA Controller
DMA Controller
DMA Controller
Interrupt Controller
Interrupt Controller
Interrupt Controller
Interrupt Controller
LPC SIO
Interrupt Controller
Interrupt Controller
Interrupt Controller
Interrupt Controller
Timer/Counter
Timer/Counter
LPC SIO
Timer/Counter
Timer/Counter
Microcontroller
Internal Unit
DMA
DMA
DMA
DMA
DMA
DMA
Interrupt
Interrupt
Interrupt
Interrupt
Forwarded to LPC
Interrupt
Interrupt
Interrupt
Interrupt
PIT (8254)
PIT
Forwarded to LPC
PIT
PIT
Forwarded to LPC
Separate
Enable/
Disable
None
None
None
None
None
None
None
None
None
None
Yes
None
None
None
None
None
None
Yes
None
None
Yes w/ 64h
Intel^® EP80579 Integrated Processor Product Line Datasheet
284
August 2009
Order Number: 320066-003US