EP80579 Datasheet, PDF (885/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
23.6.2
Error Reporting and Recovery
Error Reporting and Recovery
All errors within an HBA occur within ports. There are no errors that apply to the entire
host controller.
23.6.2.1 Error Types
23.6.2.1.1 System Memory Errors
System memory errors such as target abort, master abort, and parity may cause the
host to stop processing the currently running command. These are serious errors that
cannot be recovered from without software intervention.
A master/target abort error occurs when system software has given a pointer to the
HBA that does not exist in physical memory. When this occurs, the HBA aborts the
transfer (if necessary). When this is complete, the HBA sets PxIS.HBFS. If PxIE.HBFE
and GHC.IE are set, the HBA shall also generate an interrupt.
A data error (such as CRC or parity), may or may not be transient. If the error occurred
on a fetch of a CFIS, PRD entry or command list, the HBA shall stop. If the error
occurred on a data FIS or the ACMD field, the HBA is allowed to stop, but may also
continue. When a data error occurs, the HBA aborts the transfer (if necessary). When
this is complete, the HBA sets PxIS.HBDS. If PxIE.HBDE and GHC.IE are set, the HBA
shall also generate an interrupt.
If the HBA continue after a data error on a data or ACMD field, it shall poison the CRC
of the Data FIS it transfers to the device.
23.6.2.1.2 Interface Errors
Interface errors are errors that occur due to electrical issues on the interface, or
protocol miscommunication between the device and HBA. Depending on the type of
error, different bits in the PxSERR register are set. When these bits are set, either
PxIS.IFS (fatal) or PxIS.INFS (non-fatal) shall be set, and if enabled, the HBA shall
generate an interrupt.
Conditions that cause PxIS.IFS/PxIS.INFS to be set are:
— In the PxSERR.ERR field, the P bit is set to '1'
— In the PxSERR.DIAG field, the C or H bit is set to '1'
— PhyRdy drops unexpectedly
Examples of these types of errors are below, with the corresponding PxSERR bit that is
set if appropriate.
The only difference between PxIS.IFS and PxIS.INFS being set is the type of FIS that is
being transmitted/received when the error occurs. If the error occurred during a non-
Data FIS, the FIS must be retransmitted, so the error is non-fatal and PxIS.INFS is set.
If the error occurred during a Data FIS, the transfer shall stop, so the error is fatal and
PxIS.IFS is set.
In the case of a non-Data FIS error, between seeing a non-Data FIS fail and the
attempt to re-transmit, the HBA may receive other FISes from the device (this will
most likely happen when performing native command queuing commands). When this
occurs, the HBA must accept the FIS, perform the correct actions, and then retry the
failed FIS.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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