EP80579 Datasheet, PDF (199/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 7-14. Bus 0, Device 1, Function 0: Summary of EDMA Configuration Registers
Mapped Through EDMALBAR Memory BAR (Sheet 3 of 3)
Offset Start Offset End
Register ID - Description
Default
Value
C8h
CCh
D0h
D4h
D8h
DCh
E0h
E4h
E8h
ECh
100h
104h
CBh
CFh
D3h
D7h
DBh
DFh
E3h
E7h
EBh
EFh
103h
107h
“Offset C8h: CDAR3 - Channel 3 Current Descriptor Address Register” on page 673 00000000h
“Offset CCh: CDUAR3 - Channel 3 Current Descriptor Upper Address Register” on
page 674
00000000h
“Offset D0h: SAR3 - Channel 3 Source Address Register” on page 674
00000000h
“Offset D4h: SUAR3 - Channel 3 Source Upper Address Register” on page 674
00000000h
“Offset D8h: DAR3 - Channel 3 Destination Address Register” on page 675
00000000h
“Offset DCh: DUAR3 - Channel 3 Destination Upper Address Register” on page 675 00000000h
“Offset E0h: NDAR3 - Channel 3 Next Descriptor Address Register” on page 675 00000000h
“Offset E4h: NDUAR3 - Channel 3 Next Descriptor Upper Address Register” on
page 676
00000000h
“Offset E8h: TCR3 - Channel 3 Transfer Count Register” on page 676
00000000h
“Offset ECh: DCR3 - Channel 3 Descriptor Control Register” on page 677
00000000h
“Offset 100h: DCGC - EDMA Controller Global Command” on page 677
00000000h
“Offset 104h: DCGS - EDMA Controller Global Status” on page 678
00000000h
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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