EP80579 Datasheet, PDF (590/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 16-213.Offset 148h: PEAERRDOCMD - PCI Express Error Do Command Register
(Sheet 2 of 2)
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: 0:2:0
Offset Start: 148h
Offset End: 14Bh
View: PCI 2
BAR: Configuration
Bus:Device:Function: 0:3:0
Offset Start: 148h
Offset End: 14Bh
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
15
14
13 : 12
11 : 10
09 : 08
07 : 06
05 : 04
03 : 02
01 : 00
Bit Acronym
Bit Description
Sticky
EHLULPE
PURE
PURSFE
PURSNFE
PURSCE
Reserved
RPRSFE
RPRSNFE
RPRSCE
Enable HEADER LOG use for LLE PROTOCOL ERROR:
The header log is used by PCI Express* uncorrectable
errors. This feature is used to capture the header log for
the LLE protocol error in the unit error register during
debug.
0 = Disable
1 = Enable
PCI Express* Unit report enable: This bit enables
reporting of fatal or non-fatal or correctable unit errors.
0 = Disable
1 = Enable
PCI Express* unit report steering for fatal errors:
00b= SCI
10b=SERR
01b= SMI
11b=MCERR
PCI Express* unit report steering for non-fatal
errors: 00b=SCI
10b=SERR
01b= SMI
11b=MCERR
PCI Express* unit report steering for correctable
errors: 00b=SCI
10b=SERR
01b= SMI
11b=MCERR
Reserved
Root Port report steering for fatal errors: If the
System Error on Fatal Error bit in the Root Port Control
register is set, all fatal root port errors are reported via
SERR regardless of the setting of this register. MSI Enable
takes precedence for this capability feature.
00b= SCI
01b= SMI
10b=SERR
11b=MCERR
Root Port report steering for non-fatal errors: If the
System Error on Nonfatal Error bit in the Root Port Control
register is set, all nonfatal root port errors are reported via
SERR regardless of the setting of this register. MSI Enable
takes precedence for this capability feature.
00b= SCI
01b= SMI
10b=SERR
11b=MCERR
Root Port report steering for correctable errors: If
the System Error on Correctable Error bit in the Root Port
Control register is set, all correctable root port errors are
reported via SERR regardless of the setting of this register.
Note that MSI Enable takes precedence for this capability
feature.
00b= SCI
01b= SMI
10b=SERR
11b=MCERR
Bit Reset
Value
0b
0b
00b
00b
00b
00b
00b
00b
00b
Bit Access
RW
RW
RW
RW
RW
RW
RW
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
590
August 2009
Order Number: 320066-003US