EP80579 Datasheet, PDF (37/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Contents
35.10.1.15 Offset DDh: PCP – Power Management Next Capability Pointer
Register .......................................................................................1299
35.10.1.16 Offset DEh: PMCAP - Power Management Capability ...........................1299
35.10.1.17 Offset E0h: PMCS – Power Management Control and Status
Register .......................................................................................1300
35.10.1.18 Offset E4h: SCID – Signal Target Capability ID Register ......................1300
35.10.1.19 Offset E5h: SCP – Signal Target Next Capability Pointer Register..........1301
35.10.1.20 Offset E6h: SBC – Signal Target Byte Count Register ..........................1301
35.10.1.21 Offset E7h: STYP – Signal Target Capability Type Register...................1301
35.10.1.22 Offset E8h: SMIA – Signal Target IA Mask Register.............................1302
35.10.1.23 Offset E9h: Reserved Register .........................................................1302
35.10.1.24 Offset EAh: Reserved Register .........................................................1302
35.10.1.25 Offset ECh: SINT – Signal Target Raw Interrupt Register.....................1302
35.10.1.26 Offset F0h: MCID – Message Signalled Interrupt Capability ID
Register .......................................................................................1302
35.10.1.27 Offset F1h: MCP – Message Signalled Interrupt Next Capability Pointer
Register .......................................................................................1303
35.10.1.28 Offset F2h: MCTL – Message Signalled Interrupt Control
Register .......................................................................................1303
35.10.1.29 Offset F4h: MADR – Message Signalled Interrupt Address
Register .......................................................................................1304
35.10.1.30 Offset F8h: MDATA – Message Signalled Interrupt Data Register ..........1304
35.11 IEEE 1588 Hardware Assist Unit Configuration Space: Bus M, Device 7, Function 0 1305
35.11.1 Register Details ....................................................................................1305
35.11.1.1 Offset 00h: VID – Vendor Identification Register ................................1306
35.11.1.2 Offset 02h: DID – Device Identification Register ................................1306
35.11.1.3 Offset 04h: PCICMD – Device Command Register ...............................1306
35.11.1.4 Offset 06h: PCISTS – Device Status Register .....................................1307
35.11.1.5 Offset 08h: RID – Revision ID Register .............................................1308
35.11.1.6 Offset 09h: CC – Class Code Register ...............................................1308
35.11.1.7 Offset 0Eh: HDR – Header Type Register ..........................................1309
35.11.1.8 Offset 10h: CSRBAR – Control and Status Registers Base
Address Register............................................................................1309
35.11.1.9 Offset 2Ch: SVID – Subsystem Vendor ID Register.............................1310
35.11.1.10 Offset 2Eh: SID – Subsystem ID Register..........................................1310
35.11.1.11 Offset 34h: CP – Capabilities Pointer Register ....................................1310
35.11.1.12 Offset 3Ch: IRQL – Interrupt Line Register ........................................1311
35.11.1.13 Offset 3Dh: IRQP – Interrupt Pin Register .........................................1311
35.11.1.14 Offset DCh: PCID – Power Management Capability ID Register.............1312
35.11.1.15 Offset DDh: PCP – Power Management Next Capability Pointer
Register .......................................................................................1312
35.11.1.16 Offset DEh: PMCAP – Power Management Capability Register...............1313
35.11.1.17 Offset E0h: PMCS – Power Management Control and Status
Register .......................................................................................1313
35.11.1.18 Offset E4h: SCID – Signal Target Capability ID Register ......................1314
35.11.1.19 Offset E5h: SCP – Signal Target Next Capability Pointer Register..........1314
35.11.1.20 Offset E6h: SBC – Signal Target Byte Count Register ..........................1314
35.11.1.21 Offset E7h: STYP – Signal Target Capability Type Register...................1315
35.11.1.22 Offset E8h: SMIA – Signal Target IA Mask Register.............................1315
35.11.1.23 Offset E9h: Reserved Register .........................................................1315
35.11.1.24 Offset EAh: Reserved Register .........................................................1315
35.11.1.25 Offset ECh: SINT – Signal Target Raw Interrupt Register.....................1316
35.11.1.26 Offset F0h: MCID – Message Signalled Interrupt Capability ID
Register .......................................................................................1316
35.11.1.27 Offset F1h: MCP – Message Signalled Interrupt Next Capability Pointer
Register .......................................................................................1317
35.11.1.28 Offset F2h: MCTL – Message Signalled Interrupt Control
Register .......................................................................................1317
35.11.1.29 Offset F4h: MADR – Message Signalled Interrupt Address
Register .......................................................................................1318
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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