EP80579 Datasheet, PDF (903/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
24.2.1.13 Offset 3Dh: NTPN: Interrupt Pin Register
Table 24-15. Offset 3Dh: NTPN: Interrupt Pin Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:31:3
Offset Start: 3Dh
Offset End: 3Dh
Size: 8 bit
Default: Variable
Power Well: Resume
Bit Range Bit Acronym
Bit Description
07 : 00
INTPN
Interrupt Pin: This reflects the value of D31IP.SMIP in
CMI configuration space.
Sticky
Bit Reset
Value
Bit Access
Variable
RO
24.2.1.14 Offset 40h: HCFG: Host Configuration Register
Table 24-16. Offset 40h: HCFG: Host Configuration Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:31:3
Offset Start: 40h
Offset End: 40h
Size: 8 bit
Default: 00h
Power Well: Resume
Bit Range
07 : 03
02
01
00
Bit Acronym
Bit Description
Sticky
Reserved Reserved
I2C_EN
0 = SMBus behavior
1 = Enabled to communicate with I²C devices. This
changes the formatting of some commands.
SMB_SMI_EN
0 = SMBus interrupts will not generate an SMI#
1 = Any source of an SMB interrupt is instead be routed to
generate an SMI#. Refer to Section 24.7 (Interrupts /
SMI#).
This bit needs to be set for SMBALERT# to be enabled.
HST_EN
0 = Disable the SMBus Host controller
1 = Enable. The SMB Host controller interface is enabled
to execute commands. The INTREN bit (offset
SM_BASE + 02h, bit 0) needs to be enabled for the
SMB Host controller to interrupt or SMI#. The SMB
Host controller does not respond to any new requests
until all interrupt requests have been cleared.
Bit Reset
Value
00h
0h
0h
0h
Bit Access
RW
RW
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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