EP80579 Datasheet, PDF (605/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 16-227.DCALCSR.OPMODS in DQS Cal Mode
Bit
Description
14:12
Single step fine DLL delay: This is equivalent to DRAMDLLC.SLVLEN[4:0] when running DQS cal in
single step mode
11:8
Single step coarse DLL delay: This is equivalent to DQSOFCS when running DQS cal in single step
mode.
Test point repeat number: The number of times each delay value is tested in order to reduce the
effects of noise when near a timing threshold. When the DCALCSR.BASPAT bit is set to select the
6:4 basic data pattern, this field sets the number of times to repeat, with zero setting a max repeat value
of 8. When the extended data pattern is selected, the max repeat value becomes 15. The max repeat
is still selected with a value of zero, and other values result in a number of repeats equal to 2x-1.
Table 16-228.DCALCSR.OPMODS in Error Monitor/Read DDRIO FIFO Mode
Bit
14:3
2:0
Reserved
DDRIO FIFO Entry number.
000: Entry 0
001: Entry 1
010: Entry 2
011: Entry 3
100: Entry 4
Others: Reserved
Description
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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