EP80579 Datasheet, PDF (974/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
When C_ERR decrements to zero, the Active bit in the TD is cleared, the Stalled bit is
set, the USB Error Interrupt bit in the HC Status register is set to 1 at the end of the
frame and a hardware interrupt is signaled to the system.
25.10.2.7 Bit Stuff Error
A bit stuff error results from the detection of a sequence of more that six 1s in a row
within the incoming data stream. This will cause the C_ERR field of the TD to be
decremented. When the C_ERR field decrements to 0, the Active bit in the TD is cleared
to 0, the Stalled bit is set to 1, the USB Error Interrupt bit in the HC Status register is
set to 1 at the end of the frame and a hardware interrupt is signaled to the system.
25.10.3
Non-Transaction Based Interrupts
If a CMI process error or system error occur, the CMI halts and immediately issues a
hardware interrupt to the system.
25.10.3.1 Resume Received
This event indicates that the CMI received a RESUME signal from a device on the USB
bus during a global suspend. If this interrupt is enabled in the Interrupt Enable register,
a hardware interrupt will be signaled to the system allowing the USB to be brought out
of the suspend state and returned to normal operation.
25.10.3.2 Process Error
The HC monitors certain critical fields during operation to ensure that it does not
process corrupted data structures. These include checking for a valid PID and verifying
that the MaxLength field is less than 1280. If it detects a condition that would indicate
that it is processing corrupted data structures, it immediately halts processing, sets the
HC Process Error bit in the HC Status register and signals a hardware interrupt to the
system.
This interrupt cannot be disabled through the Interrupt Enable register.
25.10.3.3 Host System Error
The CMI sets this bit to 1 when a Parity Error, Master Abort, or Target Abort occurs on
memory accesses. When this error occurs, the CMI clears the Run/Stop bit in the
Command register to prevent further execution of the scheduled TDs. This interrupt
cannot be disabled through the Interrupt Enable register.
25.10.3.4 Implementation Notes
1. If a bad PID is found, but the packet will not be run because there is not enough
time left in the frame due to the size of the transfer or the packet time out, an error
will not be flagged.
2. “If a bad PID is found, but the packet will not be run because the TD’s active bit is
off, the host controller will not halt, and an error will not be flagged.”
25.11
USB Power Management
The Host Controller can be put into a suspended state and its power can be removed.
This requires that certain bits of information are retained in the resume power plane of
the CMI so that a device on a port may wake the system. Such a device may be a fax-
modem, which will wake up the machine to receive a fax or take a voice message.
Intel^® EP80579 Integrated Processor Product Line Datasheet
974
August 2009
Order Number: 320066-003US