EP80579 Datasheet, PDF (1342/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
37.1.1.4
37.1.1.5
37.1.1.6
Memory Alignment Terminology
Some GbE data structures have special memory alignment requirements. This implies
that the starting physical address of a data structure must be aligned as specified in
this GbE chapter. The following terms are used for this purpose:
• BYTE alignment implies that the physical addresses can be odd or even. Examples:
0FECBD9A1h, 02345ADC6h.
• WORD alignment implies that physical addresses must be aligned on even
boundaries; i.e., the last nibble of the address may only end in 0, 2, 4, 6, 8, Ah, Ch,
or Eh. For example, 0FECBD9A2h.
• DWORD (Double-Word) alignment implies that the physical addresses may only be
aligned on 4-byte boundaries; i.e., the last nibble of the address may only end in 0,
4, 8, or Ch. For example, 0FECBD9A8h.
• QWORD (Quad-Word) alignment: Implies that the physical addresses may only be
aligned on 8byte boundaries; i.e., the last nibble of the address may only end in 0,
or 8. For example, 0FECBD9A8h.
• PARAGRAPH alignment implies that the physical addresses may only be aligned on
16-byte boundaries; i.e., the last nibble must be a 0. For example, 02345ADC0h.
Alignment and Byte Ordering
It should be noted that the data stream in Ethernet has no notion of byte alignment. All
data on the wire is referenced as bit ordered. Data is presented “on the wire” least
significant bit (lsb) first.
For example: A big-endian destination address in the Ethernet header may be
represented in as 0x00_11_22_33_44_55. In this case, the data is seen on the wire in
the byte order as written from left to right, however the bits are seen lsb first, i.e. bit 0
of the first “00” byte occurs first.
Representations of these fields internal to the EP80579 may reverse the byte ordering
as shown above. Care must be taken to avoid byte ordering errors when programming
the device.
Refer to Section 37.5.14, “Endianness” on page 1422 and Section 3.6, “Endianness” on
page 119.
Packet Buffer
The GbE Packet Buffer (PB) is an ECC protected 64KB dedicated memory used for
buffering transmit and receive packets as they are communicated. The proportions of
the PB dedicated to TX and RX operations is software configurable.
Throughout this chapter, the TX portion of PB is referred to as the TX FIFO and the RX
portion of the PB is referred to as the RX FIFO. These terms are interchangeable.
It is also worthwhile to note that any information in the PB, either for incoming or
outgoing data, is volatile. The GbE will receive packets into the RX PB and transfer the
RX descriptor(s) and payload into host memory for the host CPU before sending
interrupt notification. Conversely, the host CPU will transfer TX descriptor(s) and
payload into host memory for the GbE before notifying the GbE that the packet
information is available. After this notification, the GbE transfers the TX information to
the TX PB and sends the data out on the wire. The host CPU will never have to directly
access the GbE’s PB, however diagnostic access is supported.
Intel^® EP80579 Integrated Processor Product Line Datasheet
1342
August 2009
Order Number: 320066-003US