EP80579 Datasheet, PDF (274/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
10.1.4
See Section 16.1.1.17, “Offset 59h: PAM0 - Programmable Attribute Map 0 Register”
through Section 16.1.1.23, “Offset 5Fh: PAM6 - Programmable Attribute Map 6
Register” for more register information on PAM memory space registers.
TSEG SMM Memory Space
Table 10-6. TSEG SMM Memory Space
From
TSEGSMM
TOLM - TSEG
To
TOLM
The TSEG SMM space allows system management software to partition a region of main
memory just below the top of low memory (TOLM) that is accessible only by system
management software.
Size
128kB, 256kB, 512kB, or 1 MByte in size, depending upon the
EXSMRC.TSEG_SZ field (see Section 16.1.1.25).This space
must be below 4 GBytes, so it is specified relative to TOLM and
not relative to the top of physical memory.
Enabling
SMM memory is globally enabled by EXSMRC.G_SMRAME (see
Section 16.1.1.25). Requests may access SMM system memory
when either SMM space is open (see SMRAM.D_OPEN in
Section 16.1.1.26) or the IMCH receives an SMM code request
on its processor bus.
Access
In order to access the TSEG SMM space, the TSEG must be
enabled by EXSMRC.T_EN (Section 16.1.1.25). When all of
these conditions are met, then a processor bus access to the
TSEG space (between TOLM-TSEG and TOLM) is sent to system
memory. If the high SMRAM is not enabled or if the TSEG is not
enabled, then all memory requests from all interfaces are
forwarded to system memory. If the TSEG SMM space is
enabled, and an agent attempts a non-SMM access to TSEG
space, then the transaction is specially terminated.
Inbound accesses from NSI or PCI Express ports are not allowed to access SMM space.
10.1.5 PCI Express Enhanced Configuration Aperture
Table 10-7. PCI Express Enhanced Configuration Aperture
From
To
HECREGION
0_E000_0000
0_EFFF_FFFF
PCI Express defines a memory-mapped aperture mechanism through which to access 4
Kbyte of PCI configuration register space for each possible bus, device, and function
number. This 4 Kbyte space includes the compatible 256 B of register offsets that are
traditionally accessed via the legacy CF8/CFC configuration aperture mechanism in I/O
address space, making the enhanced configuration mechanism a full superset of the
legacy mechanism. The enhanced mechanism has the advantage that full destination
and type of access is specified in a single memory-mapped uncacheable transaction on
the FSB, which is both faster and more robust than the historical I/O-mapped address
and data register access pair.
Intel^® EP80579 Integrated Processor Product Line Datasheet
274
August 2009
Order Number: 320066-003US