EP80579 Datasheet, PDF (259/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
9.4.4.1
9.4.4.2
9.5
9.5.1
9.5.2
register space is accessible from the system management bus (SMBus) to facilitate
system management. The IMCH supports ACPI power management, PCI Express native
hot-plug, and wake-from-LAN to maximize platform stand-by flexibility.
SEC-DED ECC
The IMCH supports a standard (72-bit, non-interleaved) single error correction (SEC)
and double error detection (DED) ECC mechanism for the DDR memory.
The IMCH supports both ECC and non-ECC DIMMs.
For additional information see Section 11.2, “Memory Controller Feature List” on
page 289.
Integrated Memory Scrub Engine
The IMCH includes an integrated engine to walk the populated memory space
proactively seeking out soft errors in the memory subsystem. This hardware detects,
logs, and corrects any single-bit ECC errors it encounters, and logs any uncorrectable
errors it encounters. Both types of errors may be reported via multiple alternate
mechanisms under configuration control. The scrub hardware will also execute
“demand scrub” writes when correctable errors are encountered during normal
operation (on demand reads, rather than scrub-initiated reads). This functionality
provides incremental protection against time-based deterioration of soft memory errors
from correctable to uncorrectable.
An uncorrectable error encountered by the memory scrub engine is a “speculative
error.” This designation is applied because no system agent has specifically requested
use of the corrupt data, and no real error condition exists in the system until that
occurs. It is possible that the error resides in an unmodified page of memory that is
simply dropped on a swap back to disk. If that were to occur, the speculative error
would simply “vanish” from the system without any adverse consequences.
IMCH Feature List
This section provides an overview of the major IMCH architectural features. Detailed
usage information and operational flows, internal register bit information and other
specific details of the implementation are provided later in this document.
Memory Interface
For additional information see Section 11.2, “Memory Controller Feature List” on
page 289.
PCI Express Interface in IMCH
• Support for one x8 PCI Express dual-simplex, high-speed serial I/O interface with
eight striped differential pairs in each direction (outbound and inbound)
— The interface may be unpopulated; connected to PCI, Ethernet, I/O Processor,
Infiniband* bridge devices, External bridge devices (PCI or PCI-X Gigabit
Ethernet or RAID storage devices); or connected to any other device compliant
with the same revision of the PCI Express Specification as CMI.
— The x8 interface is capable of bifurcation into two logically independent x4
interfaces with full specification compliance at half the bandwidth capability
• This interface is referred to throughout this document as the PCI Express Port A
(PEA). When configured as x8, the reference is PEA. When in x4 mode there are
two available x4 ports referred to as PEA0 and PEA1.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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