EP80579 Datasheet, PDF (624/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.5.1.30 Offset F8h: DRAMISCTL - Miscellaneous DRAM DDR Cluster Control
Register
Table 16-253.Offset F8h: DRAMISCTL - Miscellaneous DRAM DDR Cluster Control Register
Description: DRAMISCTL: Miscellaneous DRAM DDR Cluster Control Register
View: PCI
BAR: SMRBASE
Bus:Device:Function: 0:0:0
Offset Start: F8h
Offset End: FBh
Size: 32 bit
Default: 1011h
Power Well: Core
Bit Range
31 :13
12 12
11 11
10 8
Bit Acronym
Bit Description
Sticky
Reserved Reserved
N
Reserved Reserved
Y
Reserved Reserved
N
Reserved_RW
Reserved for future use. These bits are RW but SW should
not change the default reset value of these bits.
N
Vref selection: Adjustable VREF voltage at receivers. The
threshold voltage at receiver can be raised or lowered to
allow the noise margin on the data from memory be
skewed.
Bit Reset
Value
0b
1b
0b
000b
Bit Access
RO
RW
RW
RW
Vref is estimated with the following equation
Vref = (SQU * VCCDDR + (SQD – SQU) * 0.45) / (SQU +
SQD) + VOFF
where,
SQU = SQRT(4*VREFSEL<7> + 2*VREFSEL<6> +
VREFSEL<5> + 8*VREFSEL<4>)
SQD = SQRT(4*VREFSEL<3> + 2*VREFSEL<2> +
VREFSEL<1> + 8*VREFSEL<0>)
VOFF = offset, varying for each chip, nominal value is 0
but can be up to +/- 0.1V
7 :0
VREFSEL
Examples with VCCDDR=1.8V and VOFF=0
.VREFSEL. Vref (V)
00010001 0.9
00010011 0.887
00010101 0.875
00011001 0.855
11101001 0.840
11001001 0.823
10001001 0.779
00110001 0.913
01010001 0.925
10010001 0.945
10011110 0.960
10011100 0.977
10011000 1.021
Y
11h
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
624
August 2009
Order Number: 320066-003US