EP80579 Datasheet, PDF (163/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
6.1.1.5
6.1.1.6
6.1.2
6.1.2.1
6.1.2.2
S-state Wake Events
Wake events for the various ACPI sleep states cause a hard reset to the EP80579 (See
Section 27.6.3, “Exiting Sleep States” ). Wake on LAN, supported by the GbE MACs,
leverages mechanisms provided for GPI and PME wake events.
Targeted Reset Implementation
The targeted reset is provided for hot-plug events, as well as for port specific error
handling under MCA or SMI software control.
A targeted reset may be requested by setting bit six (Secondary Bus Reset) of the
Bridge Control register (D2, F0, offset 3Eh) in the target root port device. Setting this
bit crashes the Link Training and Status State machine (LTSSM) of the target port to
the reset state, where it issues at least 1024 TS1 ordered sets with the reset bit
asserted. This propagates an in-band “hot” reset to the downstream device, and
consequently force an equivalent reset to any devices further downstream. This reset is
identical to a general hard reset from the perspective of destination PCI Express*
device.
Platform Reset and Powergood
This section describes the reset and powergood external platform interfaces.
Platform Powergood
The EP80579 receives two powergood signals from the platform. The first is
CPU_VRD_PWR_GD and the other is SYS_PWR_OK. SYS_PWR_OK is asserted after a
fixed delay from the time that CPU_VRD_PWR_GD goes active and indicates that power
has been stable for at least 99 ms. The EP80579 inputs PWRGD, PWROK, and
SYS_PWR_OK are connected to the SYS_PWR_OK platform signal. CPU_VRD_PWR_GD
and SYS_PWR_OK distribution inside the EP80579 is discussed in Section 6.1.2.3,
“Reset and Powergood Distribution”. Refer to Figure 6-1 for the block diagram showing
CPU_VRD_PWR_GD and SYS_PWR_OK interfaces.
Platform Reset
The EP80579 receives two reset signals from the platform. The first one is SYS_RESET
which includes the reset button on the platform. The second is Resume Reset which is
used for resetting the IICH resume well after power is restored from a power failure.
Reset distribution inside the EP80579 is discussed in Section 6.1.2.3, “Reset and
Powergood Distribution”. Refer to the Figure 6-1, for a block diagram showing the reset
interface.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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