EP80579 Datasheet, PDF (1631/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
41.5.2.4
41.5.2.5
Delay_Response Messages
The Time Sync logic performs no action related to Delay_Response messages. It is the
responsibility of the SW for the Master to read the RECV_Snapshot register and send
the Delay_Response message containing this timestamp.
Error Handling
The time synchronization hardware depends on software for filtering appropriate IEEE-
1588 packets. When the software receives a Sync or Delay Request message, it
interrogates the 1588 hardware for time snapshot information. However before using
this data, the software must do several reasonableness checks on the data. This is due
to the possibility of lost messages, the limited 1588 queue size of 1 entry, the
possibility of multiple domains (the 1588 hardware only supports 1 domain), the
asynchronous nature of the software clearing the timestamp lock with respect to
possible incoming messages, and other similar events. Therefore the hardware includes
some mechanisms to assist the software filtering, such as the capture of the UUID and
Sequence Count.
When a time sync message is received by software that is expected to have an
associated timestamp, the software should perform the following checks:
1. Compare snapshot UUID to UUID in received 1588 packet.
2. Compare snapshot Sequence Count to Sequence Count in received 1588 packet.
3. Verify that timestamp is different than last timestamp.
If any of these tests fail, the software should clear the lock and discard the information.
41.5.3
41.5.3.1
IEEE1588 over Ethernet
Timestamping Mechanism
Per the 1588 specification, synchronized time is referenced to the end of the “start of
frame delimiter” (SFD) as shown Figure 41-5.
The time sync hardware captures the system time immediately upon detection of the
SFD. The timestamp point is immediately after the SFD. This timestamp is stored in the
snapshot register and is frozen in the snapshot register when the last nibble of the
frame CRC is transmitted or received and the overall message is detected with no
errors. If an errored frame is detected (TX_ERR or RX_ERR are asserted) then the
frame/message will be ignored.
Due to PHY and synchronization delays, the actual timestamp will be slightly later than
the desired reference point. However, allowing for 1 pclk synchronization jitter, this is
a fixed delay, easily nulled out in the software portion of the algorithm. This fixed delay
is dependent on the 10/100/1000 MHz selection at the PHY. Therefore, a constant can
be subtracted from the snapshot to compensate for PHY and synchronization delays to
arrive at the IEEE-1588 specified time stamp point.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
1631