EP80579 Datasheet, PDF (1584/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
39.5.4
one is found that is already full (MsgAv=’1’) and the link flag is set (BufferLink=’1’), the
search for a valid receive buffer is continued. If no other buffer is found, then the
RxMsgLoss interrupt is set anyway.
It is possible to build several message arrays. Each of these arrays must use the same
AMR and ACR.
TxMessage Registers
Eight transmit message holding buffers are provided. An internal priority arbiter selects
the message according to the chosen arbitration scheme. Upon transmission of a
message or message arbitration loss, the priority arbiter re-evaluates the message
priority of the next message.
Figure 39-9. Message Arbitration
Internal
Bus
Internal
Bus
Coupler
TxMessage0
TxMessage1
Txreq
Txreq
TxMessage7
RxMessage0
Txreq
Priority
Arbiter
RTRreq
RTRreq
RxMessage15
iniCAN
CANbus
Note:
The priority arbiter supports round robin and fixed priority arbitration. The arbitration
mode is selected using the configuration register.
• Round Robin - Buffers are served in a defined order: 0-1-2..7-0-1... A particular
buffer is only selected if its TxReq flag is set. This scheme guarantees that all
buffers receive the same probability to send a message.
• Fixed priority - Buffer 0 has the highest priority. With this mode, it is possible to
designate buffer 0 as the buffer for error messages and it is guaranteed that they
are sent first.
RTR message requests are served before TxMessage buffers are handled (e.g.
RTRreq0, ... RTRreq15, TxMessage0, TxMessage0, TxMessage1, ... TxMessage7).
See the description of the configuration register in the TxMessage0 Buffer in “Offset
00000020h: TxMessageControl[0-7] - Transmit Message Control and Command” for
information about how to select these modes.
Intel^® EP80579 Integrated Processor Product Line Datasheet
1584
August 2009
Order Number: 320066-003US