EP80579 Datasheet, PDF (862/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 23-61. Offset 114h: PxIE[0-1] – Port [0-1] Interrupt Enable Register (Sheet 2 of 2)
Description:
View: PCI
BAR: ABAR
Bus:Device:Function: 0:31:2
Offset Start: 114h, 194h
Offset End: 117h, 197h
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
28
27
26
25
24
23
22
21 : 08
07
06
05
04
03
02
01
00
Bit Acronym
Bit Description
Sticky
HBDE
IFE
INFE
Reserved
OFE
Reserved
PRCE
Reserved
DIE
PCE
DPE
UFE
SDBE
DSE
PSE
DHRE
Host Bus Data Error Enable (HBDE): when set, GHC.IE
is set, and P0IS.HBDS is set, the HBA shall generate an
interrupt.
Interface Fatal Error Enable (IFE): When set, GHC.IE
is set, and P0IS.IFS is set, the HBA shall generate an
interrupt.
Interface Non-fatal Error Enable (INFE): When set,
GHC.IE is set, and P0IS.INFS is set, the HBA shall
generate an interrupt.
Reserved
Overflow Enable (OFE): When set, and GHC.IE and
P0IS.OFS are set, the HBA shall generate an interrupt.
Reserved.
PhyRdy Change Interrupt Enable (PRCE): When set,
and GHC.IE is set, and PxIS.PRCS is set, the HBA shall
generate an interrupt.
Reserved
Device Interlock Enable (DIE): When set, and
P0IS.DIS is set, the HBA shall generate an interrupt.
For systems that do not support an interlock switch, this
bit shall be a read-only ‘0’.
Port Change Interrupt Enable (PCE): When set,
GHC.IE is set, and P0IS.PCS is set, the HBA shall generate
an interrupt.
Descriptor Processed Interrupt Enable (DPE): When
set, GHC.IE is set, and P0IS.DPS is set, the HBA shall
generate an interrupt.
Unknown FIS Interrupt Enable (UFE): When set,
GHC.IE is set, and PxIS.UFS is set to ‘1’, the HBA shall
generate an interrupt.
Set Device Bits FIS Interrupt Enable (SDBE): When
set, GHC.IE is set, and P0IS.SDBS is set, the HBA shall
generate an interrupt.
DMA Setup FIS Interrupt Enable (DSE): When set,
GHC.IE is set, and P0IS.DSS is set, the HBA shall generate
an interrupt.
PIO Setup FIS Interrupt Enable (PSE): When set,
GHC.IE is set, and P0IS.PSS is set, the HBA shall generate
an interrupt.
Device to Host Register FIS Interrupt Enable
(DHRE): When set, GHC.IE is set, and P0IS.DHRS is set,
the HBA shall generate an interrupt.
Bit Reset
Value
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
Bit Access
RW
RW
RW
RO
RW
RW
RW
RO
RW
RW
RW
RW
RW
RW
RW
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
862
August 2009
Order Number: 320066-003US