EP80579 Datasheet, PDF (824/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 23-11. Offset 10h: PCMDBA – Primary Command Block Base Address Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:31:2
Offset Start: 10h
Offset End: 13h
Size: 32 bit
Default: 00000001h
Power Well: Core
Bit Range
31 : 16
15 : 03
02 : 01
00
Bit Acronym
Bit Description
Sticky
Reserved
BAR
Reserved
RTE
Reserved
Base Address (BAR): Base address of the I/O space (8
consecutive I/O locations).
Reserved
Resource Type Indicator (RTE): Indicates a request for
IO space.
Bit Reset
Value
0h
0h
0h
1h
Bit Access
RO
RW
RO
RO
23.1.1.9
Offset 14h: PCTLBA – Primary Control Block Base Address Register
This 4-byte I/O space is used in Native Mode for the Primary Controller’s Control Block.
Table 23-12. Offset 14h: PCTLBA – Primary Control Block Base Address Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:31:2
Offset Start: 14h
Offset End: 17h
Size: 32 bit
Default: 00000001h
Power Well: Core
Bit Range
31 : 16
15 : 02
01
00
Bit Acronym
Bit Description
Sticky
Reserved
BAR
Reserved
RTE
Reserved
Base Address (BAR): Base address of the I/O space (4
consecutive I/O locations).
Reserved
Resource Type Indicator (RTE): Indicates a request for
IO space.
Bit Reset
Value
0h
0h
0h
1h
Bit Access
RO
RW
RO
RO
23.1.1.10 Offset 18h: SCMDBA – Secondary Command Block Base
Address Register
This 8-byte I/O space is used in Native Mode for the Secondary Controller’s Command
Block.
Intel^® EP80579 Integrated Processor Product Line Datasheet
824
August 2009
Order Number: 320066-003US