EP80579 Datasheet, PDF (482/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 16-89. Offset E8h: BERRINJCTL - Buffer Error Injection Control Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:1
Offset Start: E8h
Offset End: EBh
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
31 : 19
18
17 : 00
Bit Acronym
Bit Description
Sticky
Reserved
EnDP
Reserved
Reserved
Enable/Disable data poisoning:
When = ‘0’ , Data Poisoning is disabled - When a parity
error is detected it is sent to memory with good parity. An
interrupt will be generated if enabled and not masked.
(This is the Plumas/Placer model)
NOTE: This creates a race condition between when data
could be used vs. reporting and responding to the
interrupt.
When = ‘1’, Data Poisoning is enabled - When a parity error
is detected data is sent to memory with bad parity. An
interrupt will be generated if enabled and not masked.
(This is the new Cayuse model)
NOTE: Error Injection is possible regardless of this bit
setting.
Reserved
Bit Reset
Value
00h
0b
0b
Bit Access
RW
16.2.1.36 Offset 80h: DRAM_FERR - DRAM First Error Register
This register signals the first error occurring in the memory system. Refer to Section
11.5, “Error Handling” to understand the error handling mechanism implemented in
Core.
This register stores the first error related to the DRAM Controller. Typically, only one
error bit is set in this register. However, in the case of multiple errors in the same cycle,
multiple bits can be set in this register.
No further error bits in the DRAM_FERR register are set until the existing error bit is
cleared by software. Any future errors (NEXT errors) are set in the DRAM_NERR
register defined in Table 16-91.
The bits defined in this register are sticky through reset. Software clears these bits by
writing a 1 to the bit location.
The errors in this register are reported up into the GLOBAL_FERR registers as either
“fatal” or “non-fatal” errors from the memory controller as noted in the descriptions
below.
Note:
All memory controller errors are “not-fatal”.
Note:
Logging of these errors can be masked only by setting the corresponding bit in Section
16.2.1.38, “Offset 84h: DRAM_EMASK - DRAM Error Mask Register”.
Intel^® EP80579 Integrated Processor Product Line Datasheet
482
August 2009
Order Number: 320066-003US