EP80579 Datasheet, PDF (910/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 24-20. Offset 02h: HCTL: Host Control Register (Sheet 3 of 4)
Description:
View: PCI
BAR: SM_BASE (IO)
Bus:Device:Function: 0:31:3
Offset Start: 02h
Offset End: 02h
Size: 8 bit
Default: 00h
Power Well: Resume
Bit Range
04 : 02
Bit Acronym
Bit Description
Sticky
SMB_CMD
As shown by the bit encoding below, indicates which
command is to be performed. If enabled, the CMI
generates an interrupt or SMI# when the command has
completed If the value is for a non-supported or
reserved command, the CMI will sets the device error
(DEV_ERR) status bit and generates an interrupt when
the start bit is set. The CMI performs no command, and
does not operate until DEV_ERR is cleared.
Bits Name
Command Description
000
Quick
The slave address and read/write value (bit
0) are stored in the tx slave address register.
This command uses the transmit slave
001
Byte
address and command registers. Bit 0 of the
slave address register determines if this is a
read or write command.
This command uses the transmit slave
010
Byte
Data
address, command, and DATA0 registers. Bit
0 of the slave address register determines if
this is a read or write command. If it is a read,
the DATA0 register contains the read data.
This command uses the transmit slave
address, command, DATA0 and DATA1
011
Word
Data
registers. Bit 0 of the slave address register
determines if this is a read or write command.
If it is a read, after the command completes
the DATA0 and DATA1 registers contain the
read data.
This command uses the transmit slave
address, command, DATA0 and DATA1
Proce registers. Bit 0 of the slave address register
100 ss determines if this is a read or write command.
Call After the command completes, the DATA0
and DATA1 registers will contain the read
data.
This command uses the transmit slave
address, command, and DATA0 registers,
and the Block Data Byte register. For block
write, the count is stored in the DATA0
register and indicates how many bytes of
data will be transferred. For block reads, the
101 Block count is received and stored in the DATA0
register. Bit 0 of the slave address register
selects if this is a read or write command. For
writes, data is retrieved from the first n (where
n is equal to the specified count) addresses
of the SRAM array. For reads, the data is
stored in the Block Data Byte register.
This command uses the transmit slave
address, command, DATA0, DATA1 registers,
110
I²C
Read
and the Block Data Byte register. The read
data is stored in the Block Data Byte register.
The CMI will continue reading data until the
NAK is received.
Bit Reset
Value
000h
Bit Access
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
910
August 2009
Order Number: 320066-003US