EP80579 Datasheet, PDF (1635/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Note:
41.5.5
Note:
serviced, which may come as often as the minimum frame size. These requirements
should be easily met since CAN is a half duplex protocol operating at a relatively low
baud rate.
When a CAN packet is received or transmitted, the interrupt signal from the CAN device
will assert and cause a snapshot of system time to be captured in the TS_CanSnapLo
and TS_CanSnapHi registers. The TS_CanSnapLo register contains the lower 32 bits
of the time value, and the TS_CanSnapHi register contains the upper 32 bits. The
interrupt signal from the CAN must be enabled to assert on receive and transmit
completion of each packet in order to capture snapshots for CAN packets. It is up to the
firmware to assemble the packets into messages and determine which packet's
snapshot is the appropriate one for the entire message. There is one pair of CAN
snapshot registers (low and high) for each CAN device.
Therefore, for each CAN device, the assertion of the CAN interrupt signal when a frame
transmit or receive is completed will capture the system time in a 64-bit snapshot
register for that CAN device. Each frame that is received or transmitted will have a
snapshot taken. Firmware will process the frames as part of the overall message
evaluation, identify valid time sync messages, and determine the appropriate snapshot
to utilize. Two CAN channels are currently supported.
In order to Timestamp CAN activity the following assumptions must be valid.
• The CAN interrupts from the CAN controller MUST be serviced by Software before
the next CAN frame is detected. The initial assertion of the interrupt signal will
initiate a time snapshot of the first frame but no further snapshots will be taken
and no 1588 overflow will be set on any subsequent frames. However, this
condition is detected, not by the 1588 block but by the CAN controller itself. The
primary detection of a missed CAN interrupt is still (and always was) an overrun
condition in the CAN controller.
• In1588 mode, it is expected that only one of the 16 available CAN receive buffers
will be enabled and used. The relatively slow speed of the CAN channel makes this
an acceptable trade-off between hardware and performance. When a frame is
received, the CAN controller sets the buffer's MsgAv bit. If another frame is
received and no receive buffers are available (as would be the case if only one
buffer was enabled and its MsgAv bit was set from a previous frame not yet
serviced), the RxMsgLost flag is set in the CAN IP. Thus the software would
recognize this overflow condition by the RxMsgLost flag when it finally got around
to servicing the interrupt.
Auxiliary Snapshots
Time stamps may also be taken based on externally provided signals (asmssig and/or
ammssig). These time stamps are recorded in the auxiliary snapshot registers.
When the signal is asserted the hardware will take a timestamp and set the lock.
Software may then be notified via interrupt (if so configured) and it will read the
appropriate register. If the software clears the lock before the signal is de-asserted,
then a second, redundant snapshot event will be generated.
Hardware filtering and edge-detection were considered but not implemented because
the signal quality from the master could be bad enough to cause spurious locks. For
example, cables to a GPS could be a kilometer or more in length and the type of cable
could be a factor as well. The firmware handles the filtering and MUST not clear the lock
until after the master has negated the snapshot input.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
1635