EP80579 Datasheet, PDF (976/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 25-33. USB Legacy Keyboard/Mouse Control Register Bit Implementation (Sheet 2 of
2)
Bit #
Bit Name
Summary
Details
This bit in all host controllers will be set at the same time and
8
SMI Caused by Port 60 Read
Logically 1 bit for all
controllers
cleared at the same time. It is cleared whenever software
writes a 1 to this bit in any of the classic USB host controllers.
This bit may either be implemented separately for each
controller or shared and aliased.
This bit enables the generation of the SMI based on bit 15
7
SMI at End of Pass-Through
Enable
Separate enables ORed
together
within the same function. If bit 15 is implemented as a shared/
aliased bit across all functions, then the bit 7s from all classic
USB controllers are ORed together and used to enable the SMI
based on bit 15.
6
Pass Through State
Logically 1 bit for all
controllers
This bit in all host controllers reflects the state of the Pass-
Through state machine. Software can force this bit to 0 by
clearing the A20Gate Pass-Through Enable (bit 5) in all of the
host controllers.
5
A20Gate Pass-Through
Enable
ORed together to
enable the pass-thru
state machine
If any of these bits in the classic USB host controllers is set,
then the IICH will enable the Legacy Keyboard A20Gate Pass-
through sequence. This prevents the SMI status bits (11:8)
from asserting in all controllers when the specific sequence of
I/O cycles is observed.
4
SMI on USB IRQ
Independent Enable
Each bit provides individual host control
3
SMI on Port 64 Writes
Enable
Separate enables ORed
together
Each bit enables SMI generation if the corresponding bit 11 is
set. If bit 11 is implemented as a shared/aliased bit across all
functions, then the bit 3s from all classic USB controllers are
ORed together and used to enable the SMI based on bit 11.
Each bit enables SMI generation if the corresponding bit 10 is
2
SMI on Port 64 Reads Enable
Separate enables ORed
together
set. If bit 10 is implemented as a shared/aliased bit across all
functions, then the bit 2s from all classic USB controllers are
ORed together and used to enable the SMI based on bit 10.
1
SMI on Port 60 Writes
Enable
Separate enables ORed
together
Each bit enables SMI generation if the corresponding bit 9 is
set. If bit 9 is implemented as a shared/aliased bit across all
functions, then the bit 1s from all classic USB controllers are
ORed together and used to enable the SMI based on bit 9.
Each bit enables SMI generation if the corresponding bit 8 is
0
SMI on Port 60 Reads Enable
Separate enables ORed
together
set. If bit 8 is implemented as a shared/aliased bit across all
functions, then the bit 0s from all classic USB controllers are
ORed together and used to enable the SMI based on bit 8.
Note:
The scheme described below assumes that the keyboard controller (8042 or
equivalent) is on the LPC bus.
This legacy operation is performed through SMM space. The latched SMI source (60R,
60W, 64R, 64W) is available in the Status Register. Because the enable is after the
latch, it is possible to check for other events that didn't necessarily cause an SMI. It is
the software's responsibility to logically AND the value with the appropriate enable bits.
Note:
SMI is generated before the LPC cycle completes on the IMCH/IICH interface to ensure
that the processor doesn't complete the cycle before the SMI is observed. The logic will
also need to block the accesses to the 8042.
If there is an external 8042, then this is accomplished by not activating the 8042 CS.
This is done by logically ANDing the four enables (60R, 60W, 64R, 64W) with the 4
types of accesses to determine if 8042 CS should go active. An additional term is
required for the “pass-through” case.
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Intel^® EP80579 Integrated Processor Product Line Datasheet
976
August 2009
Order Number: 320066-003US