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Intel^® EP80579 Integrated Processor
Table 18-13. Event Transitions that Cause Messages
Event
Assertion
Deassertion
Comments
INTRUDER# pin
yes
no
PROCHOT# pin
The PROCHOT# pin is isolated when the
yes
yes
core power is off, thus preventing this
event in S3,S5.
Watchdog Timer Expired
yes
no (NA)
SEND_NOW bit
yes
NA
Occurs in G0
GPIO[11]/SMBALERT# pin
yes
yes
BATLOW#
yes
yes
CPU_PWR_FLR
yes
no
Note: The GPIO[11]/SMBALERT# pin triggers an event message (when enabled by the
GPIO11_ALERT_DISABLE bit) regardless of whether it is configured as a GPI or not.
Whenever an event occurs that causes the CMI to send a new message, it increments
the SEQ[03:00] field.
If a triggering event occurs while a message is already being generated and sent, the
new event may not appear in the current message. If not, then a second message is
generated, the SEQ[03:00] field increments to report the new event.
The following rules/steps apply if the system is in a G0 state and the policy is to reboot
the system after a hardware lockup:
1. Upon detecting the lockup the SECOND_TO_STS bit is set. The CMI may send up to
one event message to the LAN. The CMI then attempts to reboot the CPU.
2. If the reboot at step 1 is successful then the BIOS must clear the SECOND_TO_STS
bit. This prevents any further messages from being sent. The BIOS may then
perform addition recovery/boot steps.
Warning:
It is important the BIOS clears the SECOND_TO_STS bit, as the alerts interfere with the
LAN device driver from working properly. The alerts reset part of the LAN and would
prevent an operating system’s device driver from sending or receiving some messages.
3. If the reboot attempt in step 1 is not successful, then the timer timeouts a third
time. At this point the system has locked up and was unsuccessful in rebooting. The
CMI does not attempt to automatically reboot again. The CMI starts sending a
message every period (30-32 seconds). This continues until some external
intervention occurs (reset, power failure, etc.).
4. After step 3 (unsuccessful reboot after third timeout), if the user presses a Power
Button Override, the system goes to an S5 state. The CMI continues sending the
messages every period.
5. After step 4 (power button override after unsuccessful reboot) if the user presses
the Power Button again, the system must wake to an S0 state and the CPU must
start executing the BIOS.
6. If step 5 (power button press) is successful in waking the system, the CMI
continues sending messages every period until the BIOS clears the
SECOND_TO_STS bit.
Warning:
It is important the BIOS clears the SECOND_TO_STS bit, as the messages interfere
with the LAN device driver from working properly. The alerts reset part of the LAN and
prevents an operating system’s device driver from sending or receiving some LAN
packets.
Intel^® EP80579 Integrated Processor Product Line Datasheet
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August 2009
Order Number: 320066-003US