EP80579 Datasheet, PDF (255/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
9.0
CMI Introduction
This section details the system architecture supported by the Memory Controller Hub
and I/O Controller Hub complex. The Memory Controller Hub and I/O Controller Hub
are referred to collectively as the CMI (IMCH and ICH).
Subsequent chapters cover the following aspects of the MCH and the ICH:
• Description of the CMI architecture.
• Descriptions of internal registers.
• Descriptions of all external interfaces.
The EP80579 is a single chip that integrates the functionality of an IA-32 core, Memory
Controller Hub, and an I/O Controller Hub (see Figure 9-1). In this document the
Memory Controller Hub and I/O Controller Hub in CMI are referred to as IMCH
(Integrated Memory Controller Hub) and IICH (Integrated I/O Controller Hub)
respectively. The IMCH and IICH units are connected internally through the NSI (North
South Interface). The NSI is an internal bus that is not externally accessible.
Figure 9-1. CMI Block Diagram
DDR2 – (400, 533, 667, 800)
Unbuffered and Registered
ECC
1X8 PCI Express
Configurable as
2X4, 2x1
x8
SMBus
4 channel
EDMA IMCH
2 CH SATA
36 GPIOs
RTC
WDT
SPI
NSI
IICH
Memory
Controller
2 DIMM Max,
2 Ranks Max
LPC Bus
2 UART’s
2 USB-2.0
SMBus
Interrupts
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
255