EP80579 Datasheet, PDF (371/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
15.0 Platform Management (IMCH)
Note:
This chapter provides an overview of the system management support provided by the
IMCH. There are two primary management support features in the IMCH:
• Integrated system management bus (SMBus) interface
• Architectural support for platform power management
Material in this chapter is specific to the IMCH and does not apply to the IICH.
15.1
Integrated SMBus Interface
The IMCH provides a fully functional System Management Bus (SMBus) target
interface, which provides direct access to all internal IMCH configuration register space.
SMBus access is available to all internal configuration registers, regardless of whether
or not the register in question is normally accessed via the memory-mapped
mechanism or the standard configuration mechanism. This provides for highly flexible
platform management architectures, particularly given a baseboard management
controller (BMC) with an integrated network interface controller (NIC) function.
15.2
SMBus Target Architecture
The SMBus target integrated into the IMCH is compatible with the System Management
Bus (SMBus) Specification, Version 2. A brief overview of the SMBus architecture is
provided below for reference.
15.2.1
15.2.1.1
High Level Operation
The SMBus interface consists of two interface pins: a clock and serial data. Multiple
initiator and target devices may be electrically present on the same pair of signals.
Each target recognizes a start signaling semantic and recognizes its own seven-bit
address to identify pertinent bus traffic. The IMCH address is hard-coded to 011_0000.
The protocol allows for traffic to stop in “midsentence,” requiring all targets to tolerate
and properly “clean up” in the event of an access sequence that is abandoned by the
initiator prior to normal completion. The IMCH is compliant with this requirement.
The protocol comprehends “wait states” on read and write operations, which the IMCH
takes advantage of to keep the bus busy during internal configuration space accesses.
SMBus Register Summary
Table 15-1 provides a quick-reference summary of the SMBus target register space.
These registers are part of the target itself and therefore not accessible by any other
means other than the direct SMBus connection.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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