EP80579 Datasheet, PDF (114/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
3.2.2
IA Platform View of Configuration
Because the IMCH and IICH blocks in the EP80579 come from an IA heritage, the
EP80579 exposes much of the functionality in these blocks through a PCI
infrastructure. The EP80579 extends this PCI infrastructure to expose the functionality
in the AIOC, as Section 3.7, “PCI Configuration” on page 119 describes.
Before describing how the AIOC integrates with the IA-based IMCH and IICH blocks, it
is helpful to consider how the PCI exposes IMCH and IICH functionality. Logically, the
software-visible sub-blocks of the IMCH and IICH materialize as PCI devices and
functions¹ on PCI bus 0 of the system through three independent address spaces:
• Configuration Space: Each function of each device has at least 256B of
configuration space that is mapped to a fixed location by the platform (PCI
Express* devices can provide for larger configuration spaces). This space provides
system software with basic information on the device and allows for device-
independent configuration.
• Memory-Mapped I/O (MMIO) and I/O Spaces: Each function of each device
can request up to six MMIO and I/O regions of device-specified sizes to be mapped
into physical address space through base address registers in the configuration
header. System software selects the base address of each region. These spaces
support device-specific operation such as access to device-specific control
registers.
Of the thirty-two possible device slots on bus 0, five slots are reserved for software-
visible blocks in the EP80579 IMCH and IICH and remainder are unused.
In general, the IMCH claims configuration accesses (i.e., those accesses that target
configuration space) to device numbers 0, 1, 2, and 3 of bus 0 and routes configuration
accesses to the remaining devices to the IICH over an internal NSI interface using Type
0 PCI configuration transactions² (see Section 13.2, “Platform Configuration Structure
Conceptual Overview” and Section 13.3, “Routing Configuration Accesses”. In the
EP80579 design, transactions to bus 0 devices that are sent through NSI to the IICH
and unclaimed by the IICH will master abort.
Figure 3-2 presents a logical view of the EP80579 infrastructure for the software-visible
blocks in the IICH and IMCH.
1. Except where the distinction is important, this document uses the term “device” to refer to both devices and functions in the
PCI sense of these words.
2. Configuration transactions take the Type 1 form while in transit through the PCI fabric to their destination bus; upon reaching
their destination bus, they become Type 0 transactions.
Intel^® EP80579 Integrated Processor Product Line Datasheet
114
August 2009
Order Number: 320066-003US