EP80579 Datasheet, PDF (1070/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 27-19. Offset 30h: SMI_EN - SMI Control and Enable Register (Sheet 3 of 3)
Description:
View: PCI
BAR: PMBASE (IO)
Bus:Device:Function: 0:31:0
Offset Start: 30h
Offset End: 30h
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
04
03
02
01
00
Bit Acronym
Bit Description
Sticky
SMI_ON_
SLP_EN
0 = Disables the generation of SMI# on SLP_EN. Note
that this bit must be 0 before the software
attempts to transition the system into a sleep state
by writing a 1 to the SLP_EN bit.
1 = A write of 1 to the SLP_EN bit (bit 13 in PM1_CNT
register) will generate an SMI#, and the system
will not transition to the sleep state based on that
write to the SLP_EN bit.
This allows the SMI# handler work around chip-level
bugs. It is expected that the SMI# handler will turn off
the SMI_ON_SLP_EN bit before actually setting the
SLP_EN bit.
LEGACY_
USB_EN
0 = Disables legacy USB circuit
1 = Enables legacy USB circuit to cause SMI#.
BIOS_EN
0 = Disables the generation of SMI# when ACPI
software writes a 1 to the GBL_RLS bit.
1 = Enables the generation of SMI# when ACPI
software writes a 1 to the GBL_RLS bit.
EOS
End of SMI. This bit controls the arbitration of the SMI
signal to the processor. This bit must be set in order to
assert SMI# low to the processor after SMI# has been
asserted previously.
0 = Once SMI# low is asserted, the EOS bit is
automatically cleared.
1 = In the SMI handler, the processor must clear all
pending SMIs (by servicing them and then clearing
their respective status bits), set the EOS bit, and
exit SMM. This will allow the SMI arbiter to reassert
SMI upon detection of an SMI event and the setting
of a SMI status bit. The SMI# signal will go inactive
for 4 PCI clocks.
GBL_SMI_EN
0 = No SMI# will be generated.
1 = Enables the generation of SMIs in the system upon
any enabled SMI event. This bit is reset by a PCI
reset event.
Note: When the SMI_LOCK bit is set, this bit cannot
be changed.
Bit Reset
Value
0h
0h
0h
0h
0h
Bit Access
RW
RW
RW
RW
RW
27.3.3.10 Offset 34h: SMI_STS - SMI Status Register
Note:
If the corresponding _EN bit is set when the _STS bit is set, CMI will cause an SMI#
(except bits 8-10, which do not cause SMI#.)
Intel^® EP80579 Integrated Processor Product Line Datasheet
1070
August 2009
Order Number: 320066-003US