EP80579 Datasheet, PDF (137/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
The address is given directly by the PCI MSI Message Address Register, mar. Finally, the
source of the MSI transaction is set to the bus/device/function number of the device
that generates the signal.
For signaling via INTx, the header identifies the interrupt line and pin that the EP80579
should use. In this case, hardware generates the appropriate transactions for INTx
upstream into the CMI. Since the INTx mechanism cannot transport any information
beyond the fact that a signal occurred, the EP80579 needs to expose enough device
state to the software stack, via device-specific control register(s), to allow software to
be able to determine both the source and cause of the interrupt. Such state would be in
addition to the generic interrupt state that each PCI device provides through its PCI
configuration header as per the PCI specification
To integrate with the existing IMCH/IICH, the signal bridge in the EP80579 will
generate four INTx signals that it tracks based on the interrupt state of the blocks from
the AIOC that can generate signals. These four INTx signals are provided to interrupt
hardware in the IA platform hardware where they are ORed with similar signals from
other agents and converted into the appropriate signaling to the IA-32 core. This
hardware will also provide a signal back to the IMCH that indicates when the local INTx
state can be deasserted.
In addition to generating any transaction(s) necessary to send the signal to the IA, the
AIOC must preserve the semantics of PCI interrupts and signals with respect to the
state in the PCI configuration headers for the AIOC devices.
• Signaling to the IA-32 core by a device should operate in accordance with the MSI
mode and configuration in the MSI capability record.
• Signaling to the IA-32 core by a device must be disabled when the interrupt disable
bit in the PCI command register is set
• The interrupt status bit in the PCI status register should reflect the status of an
INTx signal.
This preserves the PCI abstraction for AIOC devices.
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1. This assumes that the device requests exactly one message in the PCI MSI capability record [PCI_3].
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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