EP80579 Datasheet, PDF (1354/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
37.5.3.2
37.5.4
37.5.5
37.5.5.1
specifies which portions of the packet are included in the checksum calculations, and
where the calculated values are inserted, via descriptor(s). See “TCP/IP Context
Transmit Descriptor Format” on page 1369 for details.
For receives, the hardware recognizes the packet type and performs the checksum
calculations as well as error checking automatically. Checksum and error information is
provided to software via the receive descriptor(s). Refer to “Receive Packet Checksum
Off loading” on page 1363 for details.
TCP Segmentation
The GbE implements a TCP segmentation capability for transmits which allows the
software device driver to off load packet segmentation and encapsulation to the
hardware. The device driver may send the GbE the entire IP (IPv4 or IPv6), TCP, or UDP
message sent down by the NOS for transmission. The device will segment the packet
into legal Ethernet frames and transmit them on the wire. By handling the
segmentation tasks, the hardware alleviates the software from handling some of the
framing responsibilities. This reduces the overhead on the CPU for the transmission
process thus reducing overall CPU utilization. See “TCP Segmentation” on page 1380
for details.
Buffer and Descriptor Structure
Software allocates transmit and receive buffers and forms descriptors that contain
pointers to and status of those buffers. A conceptual ownership boundary exists
between the driver software and the hardware for buffers and descriptors.
Software gives hardware ownership of a queue of buffers for receive. These buffers
store data that software acquires ownership of once a valid packet arrives.
For transmit, software maintains a queue of buffers. The software “owns” a buffer until
it is ready to transmit. Software commits the buffer to the hardware at which time the
hardware “owns” the buffer until data is transmitted or loaded in the transmit FIFO.
Descriptors store information about the buffers. They contain the physical address,
length, and status information about the referenced buffer. An end-of-packet field
indicates the last buffer for a packet.
The descriptors also contain packet specific information indicating type of packet and
specific operations to perform in the context of transmitting a packet such as those for
VLAN or checksum off load support. The following sections describe descriptor structure
and operation in more detail in the context of packet transmission and reception.
Packet Reception
In the general case, packet reception consists of recognizing the presence of a packet
on the wire, performing address filtering, storing the packet in the receive data FIFO,
transferring the data to the receive buffer in host memory, updating the state of a
receive descriptor, and setting the interrupt cause register to pass ownership of the
received packet information to software.
Packet Address Filtering
Hardware stores incoming packets in host memory subject to the following filter
modes. If there is insufficient space in the receive FIFO for an incoming packet,
hardware drops the packet and indicates the missed packet in the appropriate statistics
registers.
The following filter modes are supported:
Intel^® EP80579 Integrated Processor Product Line Datasheet
1354
August 2009
Order Number: 320066-003US