EP80579 Datasheet, PDF (984/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
26.2.1.8 Offset 0Bh: BCC - Base Class Code Register
Table 26-10. Offset 0Bh: BCC - Base Class Code Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:29:7
Offset Start: 0Bh
Offset End: 0Bh
Size: 8 bit
Default: 0Ch
Power Well: Core
Bit Range
07 :00
Bit Acronym
Bit Description
Sticky
BCC
A value of 0Ch indicates that this is a Serial Bus controller.
Bit Reset
Value
0Ch
Bit Access
RO
26.2.1.9 Offset 0Dh: MLT - Master Latency Timer Register
Table 26-11. Offset 0Dh: MLT - Master Latency Timer Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:29:7
Offset Start: 0Dh
Offset End: 0Dh
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range
07 :00
Bit Acronym
Bit Description
Sticky
Because the USB 2.0 controller is internally implemented
MLT
with arbitration on an internal interface, it does not need a
master latency timer. The bits will be fixed at 0.
Bit Reset
Value
0h
Bit Access
RO
Intel^® EP80579 Integrated Processor Product Line Datasheet
984
August 2009
Order Number: 320066-003US