EP80579 Datasheet, PDF (660/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.6.1.8
Note:
Offset 1Ch: DUAR0 - Channel 0 Destination Upper Address Register
The upper address will not be used in the EP80579, which is limited to 32bit
addressing.
The Destination Upper Address Register (DUAR) contains the upper 32-bit destination
address for the current DMA transfer. This register is loaded by the IMCH when the
destination upper address field of a new chain descriptor is read.
Because the EP80579 supports 32 bit addressing only, this register needs to be set to
“0” at all times.
Table 16-304.Offset 1Ch: DUAR0 - Channel 0 Destination Upper Address Register
Description:
View: PCI
BAR: EDMALBAR
Bus:Device:Function: 0:1:0
Offset Start: 1Ch
Offset End: 1Fh
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
31 : 00
Bit Acronym
Bit Description
DUAR0
Current Destination Address: The upper 32-bit
destination memory address for the current DMA
transfer.
Sticky
Bit Reset
Value
Bit Access
0000000h
RO
Intel^® EP80579 Integrated Processor Product Line Datasheet
660
August 2009
Order Number: 320066-003US