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EP80579 Datasheet, PDF (1317/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line
Intel® EP80579 Integrated Processor
35.11.1.27 Offset F1h: MCP – Message Signalled Interrupt Next Capability Pointer
Register
Table 35-145.Offset F1h: MCP: Message Signalled Interrupt Next Capability Pointer
Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: M:7:0
Offset Start: F1h
Offset End: F1h
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range
07 : 00
Bit Acronym
Bit Description
Sticky
MCP
Next Capability Pointer: Hardwired to 0 to indicate this
is the last capability.
Bit Reset
Value
0h
Bit Access
RO
35.11.1.28 Offset F2h: MCTL – Message Signalled Interrupt Control Register
Table 35-146.Offset F2h: MCTL: Message Signalled Interrupt Control Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: M:7:0
Offset Start: F2h
Offset End: F3h
Size: 16 bit
Default: 0000h
Power Well: Core
Bit Range
15 : 09
08
07
06 : 04
03 : 01
00
Bit Acronym
Bit Description
Sticky
Reserved
MC
C64
MME
MMC
MSIE
Reserved
Per-Vector Masking Capable: Hardwired to 0 to indicate
the device is not capable of per-vector masking.
64 bit Address Capable: Hardwired to 0 to indicate the
device does not generate 64b message addresses.
Multiple Message Enable: System software writes to this
field to indicate the number of allocated messages (less
than or equal to the number of requested messages in
MMC). A value of 0 corresponds to one message.
Multiple Message Capable: System software reads this
field to determine the number of requested messages.
Hardwired to 0 to request one message.
MSI Enable: System software sets this bit to enable MSI
signaling. A device driver is prohibited from writing this bit
to mask a device’s service request.
If 1, the device can use an MSI to request service.
If 0, the device cannot use an MSI to request service.
Bit Reset
Value
0h
0h
0h
000h
000h
0h
Bit Access
RO
RO
RO
RW
RO
RW
August 2009
Order Number: 320066-003US
Intel® EP80579 Integrated Processor Product Line Datasheet
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