EP80579 Datasheet, PDF (848/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
0C
0F
10
13
14
17
SDTP
INDEX
DATA
Secondary Data Table Pointer
AHCI Register Index
AHCI Register Data
Table 23-43. Bus 0, Device 31, Function 2: Summary of SATA Controller Configuration
Registers Mapped Through LBAR I/O BAR
Offset Start Offset End
Register ID - Description
00h
00h
“Offset 00h: PCMD – Primary Command Register” on page 848
02h
02h
“Offset 02h: PSTS – Primary Status Register” on page 849
04h
07h
“Offset 04h: PDTP – Primary Descriptor Table Pointer Register” on page 849
10h
13h
“Offset 10h: INDEX – AHCI Index Register” on page 850
14h
17h
“Offset 14h: DATA – AHCI Data Register” on page 851
Default
Value
00h
00h
Variable
00000000h
Variable
23.2.1
23.2.1.1
Primary Devices
Offset 00h: PCMD – Primary Command Register
Table 23-44. Offset 00h: PCMD – Primary Command Register
Description:
View: PCI
Base Address: LBAR (IO)
Bus:Device:Function: 0:31:2
Offset Start: 00h
Offset End: 00h
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range
07 : 04
03
02 : 01
00
Bit Acronym
Bit Description
Sticky
Reserved
RWC
Reserved
START
Reserved
Read / Write Control (RWC): Sets the direction of
the bus master transfer: 0 = memory to device, 1 =
device to memory. This bit must not be changed when
the bus master function is active.
Reserved
Start/Stop Bus Master (START): Setting this bit
enables bus master operation of the controller. Bus
master operation does not actually start unless the Bus
Master Enable bit in PCI configuration space is also set.
Clearing it halts bus master operation.
All state information is lost when this bit is written to
'0'; Master mode operation cannot be stopped and then
resumed. If this bit is reset while bus master operation
is still active and the device has not yet finished its data
transfer, the bus master command is said to be aborted.
If this bit is cleared to ‘0’ prior to the DMA data transfer
being initiated by the drive in a device to memory data
transfer, then the ICH5 will not send DMAT to terminate
the data transfer. SW intervention (e.g. sending SRST)
is required to reset the interface in this condition.
This bit is intended to be cleared by software after the
data transfer is completed, as indicated by either the
ACT bit being cleared in the status register, or the I bit
being set in the status register, or both.
Bit Reset
Value
0h
0h
0h
0h
Bit Access
RO
RW
RO
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
848
August 2009
Order Number: 320066-003US