EP80579 Datasheet, PDF (1184/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
33.5.3.7
Offset 04h: MCR - Modem Control Register
This 8-bit register controls the interface with the modem or data set (or a peripheral
device emulating a modem).
Table 33-19. Offset 04h: MCR - Modem Control Register (Sheet 1 of 2)
Description:
View: IA F
Base Address: Base (IO)
Offset Start: 04h
Offset End: 04h
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range
07 :05
04
03
Bit Acronym
Bit Description
Sticky
Reserved
LOOP
OUT2
Reserved
Loop back test mode: This bit provides a local
Loopback feature for diagnostic testing of the UART.
When LOOP is set to a logic 1, the following occurs: The
transmitter serial output is set to a logic 1 state. The
OUT2# signal is forced to a logic 1 state. The receiver
serial input is disconnected from the pin. The output of
the Transmitter Shift register is “looped back” into the
receiver shift register input. The four modem control
inputs (CTS#, DSR#, DCD#, and RI#) are disconnected
from the pins and the modem control output pins (RTS#
and DTR#) are forced to their inactive state.
• Coming out of the loopback test mode may result in
unpredictable activation of the delta bits (bits 3:0)
in the Modem Status Register (MSR). It is
recommended that MSR be read once to clear the
delta bits in the MSR.
The lower four bits of the Modem Control register are
connected to the upper four Modem Status register bits:
• DTR = 1 forces DSR to a 1
• RTS = 1 forces CTS to a 1
• OUT1 = 1 forces RI to a 1
• OUT2= 1 forces DCD to a 1
In the diagnostic mode, data that is transmitted is
immediately received. This feature allows the processor
to verify the transmit and receive data paths of the
UART. The transmit, receive and modem control
interrupts are operational, except the modem control
interrupts are activated by Control register bits, not the
modem control inputs. A break signal can also be
transferred from the transmitter section to the receiver
section in loopback mode.
0 = Normal UART operation
1 = Test mode UART operation
OUT2# signal control: This bit controls the OUT2#
output. When the OUT2 bit is set, OUT2# is asserted
low. When the OUT2 bit is cleared, OUT2# is deasserted
(set high). Outside of the UART module, the OUT2#
signal is used to connect the UART's interrupt output to
the Interrupt Controller unit.
0 = OUT2# signal is 1, which disables the UART
interrupt.
1 = OUT2# signal is 0.
Bit Reset
Value
000b
0b
0b
Bit Access
RW
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
1184
August 2009
Order Number: 320066-003US