EP80579 Datasheet, PDF (997/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 26-30. Offset 6Ch: ULSCS - USB 2.0 Legacy Support Control/Status Register (Sheet 3
of 3)
Description: Lockable: Suspend well, and not D3-to-D0 warm reset nor core well.
View: PCI
BAR: Configuration
Bus:Device:Function: 0:29:7
Offset Start: 6Ch
Offset End: 6Fh
Size: 32bit
Default: 00000000h
Power Well: Suspend
Bit Range
02
01
00
Bit Acronym
Bit Description
SMI_PCEN
SMI on Port Change Enable:
0 = Disable.
1 = Enable. When this bit is a 1, and the SMI on Port
Change Detect bit (D29:F7:6Ch, bit 18) is a 1, the
host controller will issue an SMI.
SMI_USBEN
SMI on USB Error Enable:
0 = Disable.
1 = Enable. When this bit is a 1, and the SMI on USB
Error bit (D29:F7:6Ch, bit 17) is a 1, the host
controller will issue an SMI immediately.
SMI_USBCE
SMI on USB Complete Enable:
0 = Disable.
1 = Enable. When this bit is a 1, and the SMI on USB
Complete bit (D29:F7:6Ch, bit 16) is a 1, the host
controller will issue an SMI immediately.
Sticky
Bit Reset
Value
0h
0h
0h
Bit Access
RW
RW
RW
26.2.1.29 Offset 70h: ISU2SMI - Intel Specific USB 2.0 SMI Register
This register provides a mechanism for BIOS to provide USB 2.0 related bug fixes and
workarounds. Writing a ‘1’ to that bit location clears bits that are marked as Read/
Write/Clear (RW/C). Software must clear all SMI status bits prior to setting the global
SMI enable bit and individual SMI enable bit to prevent spurious SMI when returning
from a power down.
Table 26-31. Offset 70h: ISU2SMI - Intel Specific USB 2.0 SMI Register (Sheet 1 of 3)
Description: Lockable: Suspend well, and not D3-to-D0 warm reset nor core well.
View: PCI
BAR: Configuration
Bus:Device:Function: 0:29:7
Offset Start: 70h
Offset End: 73h
Size: 32 bit
Default: 00000000h
Power Well: Suspend
Bit Range
31 :30
29 :26
25 :24
23 :22
Bit Acronym
Bit Description
Sticky
Reserved
Reserved
Reserved
SMI_PO
Reserved. Hardwired to 0.
Reserved
Reserved
SMI on PortOwner: Bits 23:22 correspond to the Port
Owner bits for ports 1 (22) through 02 (23). These bits
are set to ‘1’ whenever the associated Port Owner bits
transition from 0->1 or 1->0. Software clears these bits
by writing a one.
Bit Reset
Value
00b
0000b
00b
00b
Bit Access
RW
RWC
RWC
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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