EP80579 Datasheet, PDF (786/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 21-2. GPIO Boot Source Selection
GPIO17
1
0
GPIO33
1
1
Description
Default. Boot from LPC
Reserved.
1
0
Reserved.
0
0
Boot from SPI
21.3
21.3.1
SPI Protocol
Communication on the SPI bus is done with a Master – Slave protocol. Typical bus
topologies call for a single SPI Master with a single SPI Slave. The SPI interface consists
of a four wire interface: clock (CLK), master data out (Master Out Slave In (MOSI)),
master data in (Master In Slave Out (MISO)) and an active low chip select (CS#).
SPI Pin-Level Protocol
SPI communicates utilizing a synchronous protocol with the clock being driven by the
Master. After selecting a Slave by asserting the SPI_CS# signal, the Master generates
eight clock pulses per byte on the SPI_CLK wire, one clock pulse per data bit. ¹ Data
flows from master to slave on the SPI_MOSI wire and from slave to master on the
SPI_MISO wire². Data is setup and sampled on opposite edges of the SPI_CLK signal.
Master drives data off of the falling edge of the clock and slave samples on the rising
edge of the clock. Similarly, Slave drives data off of the falling edge of the clock. The
master has more flexibility on sampling schemes since it controls the clock. Note that
SPI_CLK flight times and the device SPI_MISO max valid times indicate that the rising
edge is not feasible for sampling the SPI_MISO input at the master for a 20 MHz clock
period with 50% duty cycle.
1. SPI supports 8 or 16 bit words, however all devices on the supported list only operate on 8 bit words.
2. SPI specifies that data can be shifted MSB or LSB first, however all devices on the supported list only operate MSB first.
Intel^® EP80579 Integrated Processor Product Line Datasheet
786
August 2009
Order Number: 320066-003US