EP80579 Datasheet, PDF (469/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.2.1.21 Offset 62h: FSB_NERR - FSB Next Error Register
Table 16-75. Offset 62h: FSB_NERR - FSB Next Error Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:1
Offset Start: 62h
Offset End: 63h
Size: 16 bit
Default: 0000h
Power Well: Core
Bit Range
15 : 10
09 06
05
04
03
02
01
00
Bit Acronym
Bit Description
Sticky
Reserved Reserved
Reserved Reserved
Non-DRAM Lock Error: This bit is sticky through reset.
System software clears this bit by writing a 1 to the
location.
NDLOCK _{0 = No DRAM Lock Error detected}
Y
1 = IMCH detected a lock operation to memory space that
did not map into DRAM. (NON-FATAL)
ATOM
FSB Address Above TOM/TOLM: This bit is sticky
through reset. System software clears this bit by writing a
1 to the location.
0 = No FSB address above TOM/TOLM detected
Y
1 = IMCH has detected an address above the Top of
Memory and above 4 Gbyte.If the system has less than
4 Gbyte of DRAM, then unclaimed addresses between
TOLM and 4 Gbyte are sent to NSI. (NON-FATAL)
Reserved Reserved
Y
FSB Address Strobe Glitch Detected: This bit is sticky
through reset. System software clears this bit by writing a
1 to the location.
FSBAGL
0 = No FSB address strobe glitch detected.
Y
1 = IMCH has detected a glitch one of the FSB address
strobes. (FATAL)
FSB Data Strobe Glitch Detected: This bit is sticky
through reset. System software clears this bit by writing a
1 to the location.
FSBDGL _{0 = No FSB data strobe glitch detected.}
Y
1 = IMCH has detected a glitch one of the FSB data
strobes. (FATAL)
Reserved Reserved
Y
Bit Reset
Value
00h
0000b
0b
0b
0b
0b
0b
0b
Bit Access
RWC
RWC
RWC
RWC
RWC
RWC
RWC
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
469