EP80579 Datasheet, PDF (22/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Contents
21.4.3.3 Flash Protection .............................................................................. 800
21.4.3.4 Decoding Memory Ranges for SPI ...................................................... 801
21.5 BIOS Programming Considerations ..................................................................... 801
21.5.1 SPI Initialization ..................................................................................... 801
22.0 General Purpose I/O: Bus 0, Device 31, Function 0 ................................................ 803
22.1 Overview ........................................................................................................ 803
22.1.1 GPIO Summary Table.............................................................................. 805
22.2 General Purpose I/O-Mapped Configuration Register Details .................................. 806
22.2.1 Register Descriptions .............................................................................. 807
22.2.1.1
22.2.1.2
22.2.1.3
22.2.1.4
22.2.1.5
22.2.1.6
22.2.1.7
22.2.1.8
Offset 00h: GPIO_USE_SEL1 -GPIO Use Select 1 {31:0}
Register ......................................................................................... 807
Offset 04h: GP_IO_SEL1 - GPIO Input/Output Select 1 {31:0}
Register ......................................................................................... 808
Offset 0Ch: GP_LVL1 - GPIO Level 1 for Input or Output {31:0}
Register ......................................................................................... 809
Offset 18h: GPO_BLINK - GPIO Blink Enable Register ........................... 810
Offset 2Ch: GPI_INV - GPIO Signal Invert Register .............................. 812
Offset 30h: GPIO_USE_SEL2 - GPIO Use Select 2 {63:32}
Register ......................................................................................... 813
Offset 34h: GP_IO_SEL2 - GPIO Input/Output Select 2 {63:32} Register 813
Offset 38h: GP_LVL2 - GPIO Level for Input or
Output 2 {63:32} Register ............................................................... 814
22.3 Additional GPIO Theory of Operation .................................................................. 815
22.3.1 SMI# and SCI Routing ............................................................................ 815
22.3.2 Triggering.............................................................................................. 815
23.0 SATA: Bus 0, Device 31, Function 2 ........................................................................ 817
23.1 SATA PCI Configuration Registers ...................................................................... 817
23.1.1 PCI Header ............................................................................................ 819
23.1.1.1
23.1.1.2
23.1.1.3
23.1.1.4
23.1.1.5
23.1.1.6
23.1.1.7
23.1.1.8
23.1.1.9
23.1.1.10
23.1.1.11
23.1.1.12
23.1.1.13
23.1.1.14
23.1.1.15
23.1.1.16
Offset 00h: ID - Identifiers Register ................................................... 819
Offset 04h: CMD - Command Register................................................ 819
Offset 06h: STS - Device Status Register............................................ 820
Offset 08h: RID - Revision ID Register ............................................... 821
PI - Programming Interface Register .................................................. 822
Offset 0Ah: CC - Class Code Register ................................................. 823
Offset 0Dh: MLT – Master Latency Timer Register ................................ 823
Offset 10h: PCMDBA – Primary Command Block Base Address
Register ......................................................................................... 823
Offset 14h: PCTLBA – Primary Control Block Base Address Register........ 824
Offset 18h: SCMDBA – Secondary Command Block Base
Address Register ............................................................................. 824
Offset 1Ch: SCTLBA – Secondary Control Block Base Address
Register ......................................................................................... 825
Offset 20h: LBAR – Legacy Bus Master Base Address Register ............... 825
Offset 24h: ABAR – AHCI Base Address Register.................................. 826
Offset 2Ch: SS - Sub System Identifiers Register................................. 827
Offset 34h: CAP – Capabilities Pointer Register.................................... 827
Offset 3Ch: INTR - Interrupt Information Register ............................... 828
23.1.2 Additional SFF-8038i Configuration Registers.............................................. 828
23.1.2.1
23.1.2.2
23.1.2.3
23.1.2.4
23.1.2.5
23.1.2.6
Offset 40h: PTIM – Primary Timing Register ........................................ 829
STIM – Secondary Timing Register .................................................... 830
Offset 44h: D1TIM – Device 1 IDE Timing Register .............................. 830
Offset 48h: SYNCC – Synchronous DMA Control Register ...................... 831
Offset 4Ah: SYNCTIM – Synchronous DMA Timing Register ................... 832
Offset 54h: IIOC – IDE I/O Configuration Register ............................... 833
23.1.3 PCI Power Management Capabilities .......................................................... 834
23.1.3.1 Offset 70h: Offset 70h: PID – PCI Power Management Capability ID Register
834
Intel^® EP80579 Integrated Processor Product Line Datasheet
22
August 2009
Order Number: 320066-003US