EP80579 Datasheet, PDF (445/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.2
Warning:
Note:
DRAM Controller Error Reporting Registers: Bus 0, Device
0, Function 1
The DRAM Controller Error Reporting registers are in Bus 0, Device 0, Function 1.
Table 16-54 provides the register address map for this device and function.
Address locations that are not listed are considered reserved register locations. Reads
to reserved registers may return non-zero values. Writes to reserved locations may
cause system failure.
Reserved bits are Read Only.
Table 16-54. Bus 0, Device 0, Function 1: Summary of IMCH Error Reporting PCI
Configuration Registers (Sheet 1 of 2)
Offset Start Offset End
Register ID - Description
00h
02h
04h
06h
08h
0Ah
0Bh
0Dh
0Eh
2Ch
2Eh
40h
44h
48h
4Ch
50h
54h
58h
5Ch
60h
62h
64h
68h
6Ah
6Ch
6Eh
70h
72h
74h
01h
03h
05h
07h
08h
0Ah
0Bh
0Dh
0Eh
2Dh
2Fh
43h
47h
4Bh
4Fh
53h
57h
5Bh
5Fh
61h
63h
65h
69h
6Bh
6Dh
6Fh
70h
72h
74h
“Offset 00h: VID - Vendor Identification Register” on page 447
“Offset 02h: DID - Device Identification Register” on page 447
“Offset 04h: PCICMD - PCI Command Register” on page 448
“Offset 06h: PCISTS - PCI Status Register” on page 448
“Offset 08h: RID - Revision Identification Register” on page 449
“Offset 0Ah: SUBC - Sub-Class Code Register” on page 449
“Offset 0Bh: BCC - Base Class Code Register” on page 449
“Offset 0Dh: MLT - Master Latency Timer Register” on page 450
“Offset 0Eh: HDR - Header Type Register” on page 450
“Offset 2Ch: SVID - Subsystem Vendor Identification Register” on page 450
“Offset 2Eh: SID - Subsystem Identification Register” on page 451
“Offset 40h: GLOBAL_FERR - Global First Error Register” on page 451
“Offset 44h: GLOBAL_NERR - Global Next Error Register” on page 453
“Offset 48h: NSI_FERR - NSI First Error Register” on page 454
“Offset 4Ch: NSI_NERR - NSI Next Error Register” on page 457
“Offset 50h: NSI_SCICMD - NSI SCI Command Register” on page 459
“Offset 54h: NSI_SMICMD: NSI SMI Command Register” on page 461
“Offset 58h: NSI_SERRCMD - NSI SERR Command Register” on page 464
“Offset 5Ch: NSI_MCERRCMD - NSI MCERR Command Register” on page 466
“Offset 60h: FSB_FERR - FSB First Error Register” on page 468
“Offset 62h: FSB_NERR - FSB Next Error Register” on page 469
“Offset 64h: FSB_EMASK - FSB Error Mask Register” on page 470
“offset 68h: FSB_SCICMD - FSB SCI Command Register” on page 471
“Offset 6Ah: FSB_SMICMD - FSB SMI Command Register” on page 472
“Offset 6Ch: FSB_SERRCMD - FSB SERR Command Register” on page 473
“Offset 6Eh: FSB_MCERRCMD - FSB MCERR Command Register” on page 474
“Offset 70h: BUF_FERR - Memory Buffer First Error Register” on page 475
“Offset 72h: BUF_NERR - Memory Buffer Next Error Register” on page 475
“Offset 74h: BUF_EMASK - Memory Buffer Error Mask Register” on page 476
Default
Value
8086h
5021h
0000h
0000h
Variable
00h
FFh
00h
00h
0000h
0000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
0000h
0000h
0009h
0000h
0000h
0000h
0000h
00h
00h
00h
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
445