EP80579 Datasheet, PDF (1022/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
26.5
Data Structures in Main Memory
See Section 3 and Appendix B of the EHCI Specification, Rev. 1.0 for details.
26.6
USB 2.0 Enhanced Host Controller DMA
The USB 2.0 enhanced host controller implements three sources of USB packets. They
are, in order of priority on USB during each microframe,
1. the USB 2.0 Debug Port (see Section 26.13),
2. the Periodic DMA engine, and
3. the Asynchronous DMA engine.
CMI always performs any currently-pending debug port transaction at the beginning of
a microframe, followed by any pending periodic traffic for the current microframe. If
there is time left in the microframe, then the EHC performs any pending asynchronous
traffic at the end of the microframe (EOF1). The debug port traffic is only presented on
one port (Port #0), while the other ports are idle during this time.
The following subsections describe the policies of the periodic and asynchronous DMA
engines.
26.6.1
Periodic List Execution
The Periodic DMA engine contains buffering for two control structures (two
transactions). By implementing two entries, the EHC is able to pipeline the memory
accesses for the next transaction while executing the current transaction on the USB
ports. A multiple-packet, high-bandwidth transaction occupies one of these buffer
entries, which means that up to six 1 Kbyte data packets may be associated with the
two buffered control structures.
In order to simplify the pipelined implementation that is optimized for normal
execution, the EHC does not implement immediate retries on High Bandwidth Interrupt
transactions that encounter transaction errors (for ins and outs) or a Data Toggle
mismatch (for Interrupt In). This is an optional implementation, but not recommended,
by the USB Specification and the USB Specification, Revision 0.95. The EHC will
reattempt the transaction when that qTD is encountered again in the periodic schedule.
If successful when reattempted, then the EHC will continue with the multiple packets
allowed by the high-bandwidth endpoint during that same microframe.
26.6.1.1
Read Policies for Periodic DMA
The Periodic DMA engine performs memory reads for the following structures:
Table 26-50. Periodic DMA Engine Memory Reads
Memory Structure
Periodic Frame List
entry
Frame Span
Traversal Node
iTD
siTD
Size
(DWORDS)
1
2
23
9
Comments
The EHC reads the entry for each microframe. The frame list is not
internally cached across microframes.
Only the 64-bit addressing format is supported.
Only the 64-bit addressing format is supported.
Intel^® EP80579 Integrated Processor Product Line Datasheet
1022
August 2009
Order Number: 320066-003US