EP80579 Datasheet, PDF (1310/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
35.11.1.9 Offset 2Ch: SVID – Subsystem Vendor ID Register
This register is a write-once register. Once any byte in the register has been written,
the register locks against further writes until reset.
Table 35-129.Offset 2Ch: SVID: Subsystem Vendor ID Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: M:7:0
Offset Start: 2Ch
Offset End: 2Dh
Size: 16 bit
Default: 0000h
Power Well: Core
Bit Range
15 : 00
Bit Acronym
Bit Description
Sticky
SVID
Subsystem Vendor ID: This field must be programmed
during BIOS initialization.
Bit Reset
Value
0h
Bit Access
RWO
35.11.1.10 Offset 2Eh: SID – Subsystem ID Register
This register is a write-once register. Once any byte in the register has been written,
the register locks against further writes until reset.
Table 35-130.Offset 2Eh: SID: Subsystem ID Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: M:7:0
Offset Start: 2Eh
Offset End: 2Fh
Size: 16 bit
Default: 0000h
Power Well: Core
Bit Range Bit Acronym
Bit Description
15 : 00
SID
Subsystem ID: This field must be programmed during
BIOS initialization.
Sticky
Bit Reset
Value
Bit Access
0h
RWO
35.11.1.11 Offset 34h: CP – Capabilities Pointer Register
Table 35-131.Offset 34h: CP: Capabilities Pointer Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: M:7:0
Offset Start: 34h
Offset End: 34h
Size: 8 bit
Default: DCh
Power Well: Core
Bit Range Bit Acronym
Bit Description
07 : 00
Pointer to First Capability Structure: Value is DCh
CP
which is the config space offset of the first capability
structure.
Sticky
Bit Reset
Value
Bit Access
DCh
RO
Intel^® EP80579 Integrated Processor Product Line Datasheet
1310
August 2009
Order Number: 320066-003US