EP80579 Datasheet, PDF (142/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
The actions taken by the hardware in response to an error event depends on the
manner in which software has configured the IMCH to report the error. For unmasked
events that the IMCH signals through SMI, SCI, or SERR, the IMCH presents the error
to the IA-32 core indirectly through the IICH. In these cases, the IMCH sends an error
message to the IICH (via NSI) that IICH interrupt logic handles by signaling the IA-32
core through an interrupt. For unmasked events that the IMCH signals through MCERR,
the IMCH directly presents the error to the IA-32 core (via FSB). In this case, the IMCH
directly signals the IA-32 core through the MCERR protocol on the FSB.
After receiving the message, software will query the global IMCH error registers (see
Section 5.3.2, “Global Error Events”) to determine which IMCH unit is responsible for
the error. With that information, software can query the unit that generated the event
to determine the specific cause.
5.3.2
Global Error Events
.
Table 5-1.
Table 5-1 summarizes the error events that the IMCH captures in its GLOBAL_FERR and
GLOBAL_NERR error registers (see Section 16.2.1.12, “Offset 40h: GLOBAL_FERR -
Global First Error Register” and Section 16.2.1.13, “Offset 44h: GLOBAL_NERR - Global
Next Error Register”). Each of these events rolls up one or more unmasked error events
from an individual IMCH unit. To determine the specific error event that causes a
signal, software consults the unit-specific error registers that Table 5-1 indicates. The
global registers provide summary information only; masking takes place at the unit
level.
Summary of IMCH Global Error Conditions
Event
Fatality^a
Unit-Specific
Registers
Notes
DRAM Controller Fatal Error
FSB Fatal Error
NSI Fatal Error
DMA Fatal Error
PCI Express* Port A1, A0 Fatal
Error
Buffer Unit Non-Fatal Error
DRAM Controller Non-Fatal Error
FSB Non-Fatal Error
NSI Non-Fatal Error
DMA Non-Fatal Error
PCI Express* Port A1, A0 Non-Fatal
Error
Fatal
Fatal
Fatal
Fatal
Fatal
Non-Fatal
Non-Fatal
Non-Fatal
Non-Fatal
Non-Fatal
Non-Fatal
DRAM_FERR,
DRAM_NERR
FSB_FERR,
FSB_NERR
NSI_FERR,
NSI_NERR
EDMA_FERR,
EDMA_NERR
PEAFERR,
PEANERR^b
BUF_FERR,
BUF_NERR
DRAM_FERR,
DRAM_NERR
FSB_FERR,
FSB_NERR
NSI_FERR,
NSI_NERR
EDMA_FERR,
EDMA_NERR
PEAFERR,
PEANERR^b
Fatal error in DRAM interface.
Fatal error on internal CPU/IMCH FSB
interface.
Fatal error on internal IMCH/IICH NSI
interface.
Fatal error from DMA controller.
Fatal error from PCI Express* Port A1
(PEA1) or A0 (PEA0).
Non-fatal error in posted memory write
buffer.
Non-fatal error in DRAM interface.
Non-fatal error on internal CPU/IMCH
FSB interface.
Non-fatal error on internal IMCH/IICH
NSI interface.
Non-fatal error from DMA controller.
Non-fatal error from PCI Express* Port
A1 (PEA1) or A0 (PEA0).
a. Fatal versus non-fatal classification for reporting through GLOBAL_FERR and GLOBAL_NERR.
b. Each port has its own independent PEAFERR and PEANERR registers in the PCI configuration space for the port
controller device.
Intel^® EP80579 Integrated Processor Product Line Datasheet
142
August 2009
Order Number: 320066-003US