EP80579 Datasheet, PDF (1038/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 26-55. Offset A0h: CNTL_STS - Control/Status Register (Sheet 2 of 2)
Description:
View: PCI
BAR: MBAR
Bus:Device:Function: 0:29:7
Offset Start: A0h
Offset End: A3h
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range Bit Acronym
Bit Description
Sticky
06
05
04
03 :00
0 = The hardware clears this bit to 0 upon the proper
ERROR_GOOD_
N_STS
1=
completion of a read or write.
The hardware sets this bit to indicate that an error
has occurred. Details on the nature of the error are
provided in the Exception field. Reset default = 0.
GO_CNT
Software sets this bit to cause the hardware to perform a
read or write request. Writing a 0 to this bit has no effect.
Writing a 1 to this bit when it is already set may result in
undefined behavior. When set, the hardware clears this bit
when the hardware sets the DONE_STS bit.
Reset default = 0.
Software sets this bit to indicate that the current request
WRITE_READ_N ^{is a write. Software clears this bit to indicate that the}
_CNT
current request is a read.
Reset default = 0.
This field is used to indicate the size of the data to be
transferred. For write operations, this field is set by
software to indicate to the hardware how many bytes of
data in Data Buffer are to be transferred to the console. A
value of 0h indicates that a zero-length packet must be
sent. A value of 1-8 indicates 1-8 bytes are to be
transferred. Values 9-Fh are illegal and how hardware
behaves if used is undefined.
For read operations, this field is set by hardware to
DATA_LEN_CNT indicate to software how many bytes in Data Buffer are
valid in response to a read operation. A value of 0h
indicates that a zero length packet was returned and the
state of Data Buffer is not defined. A value of 1-8 indicates
1-8 bytes were received. Hardware is not allowed to
return values 9-Fh.
The transferring of data always starts with byte 0 in the
data area and moves toward byte 7 until the transfer size
is reached.
Reset default = 0h.
Bit Reset
Value
0h
0h
0h
0h
Bit Access
RO
RW
RW
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
1038
August 2009
Order Number: 320066-003US